X-Git-Url: https://git.libre-soc.org/?a=blobdiff_plain;ds=sidebyside;f=src%2Famd%2Fvulkan%2Fradv_private.h;h=d6f396f0056565ad32a3eeda26ecc2dc813fe29f;hb=6880b42cfc1a1b2f30ccd02df1956a78efbe5551;hp=ddabcedc95895d6ffea03da88c0d59b298898bab;hpb=210aec3612bc02a6a02035188937a4755da5a252;p=mesa.git diff --git a/src/amd/vulkan/radv_private.h b/src/amd/vulkan/radv_private.h index ddabcedc958..d6f396f0056 100644 --- a/src/amd/vulkan/radv_private.h +++ b/src/amd/vulkan/radv_private.h @@ -48,6 +48,7 @@ #include "compiler/shader_enums.h" #include "util/macros.h" #include "util/list.h" +#include "util/xmlconfig.h" #include "main/macros.h" #include "vk_alloc.h" #include "vk_debug_report.h" @@ -90,6 +91,7 @@ typedef uint32_t xcb_window_t; #define MAX_VIEWPORTS 16 #define MAX_SCISSORS 16 #define MAX_DISCARD_RECTANGLES 4 +#define MAX_SAMPLE_LOCATIONS 32 #define MAX_PUSH_CONSTANTS_SIZE 128 #define MAX_PUSH_DESCRIPTORS 32 #define MAX_DYNAMIC_UNIFORM_BUFFERS 16 @@ -102,6 +104,8 @@ typedef uint32_t xcb_window_t; #define MAX_SO_STREAMS 4 #define MAX_SO_BUFFERS 4 #define MAX_SO_OUTPUTS 64 +#define MAX_INLINE_UNIFORM_BLOCK_SIZE (4ull * 1024 * 1024) +#define MAX_INLINE_UNIFORM_BLOCK_COUNT 64 #define NUM_DEPTH_CLEAR_PIPELINES 3 @@ -277,6 +281,9 @@ void *radv_lookup_entrypoint_checked(const char *name, uint32_t core_version, const struct radv_instance_extension_table *instance, const struct radv_device_extension_table *device); +void *radv_lookup_physical_device_entrypoint_checked(const char *name, + uint32_t core_version, + const struct radv_instance_extension_table *instance); struct radv_physical_device { VK_LOADER_DATA _loader_data; @@ -309,6 +316,9 @@ struct radv_physical_device { /* Whether LOAD_CONTEXT_REG packets are supported. */ bool has_load_ctx_reg_pkt; + /* Whether to enable the AMD_shader_ballot extension */ + bool use_shader_ballot; + /* This is the drivers on-disk cache used as a fallback as opposed to * the pipeline cache defined by apps. */ @@ -337,6 +347,9 @@ struct radv_instance { struct vk_debug_report_instance debug_report_callbacks; struct radv_instance_extension_table enabled_extensions; + + struct driOptionCache dri_options; + struct driOptionCache available_dri_options; }; VkResult radv_init_wsi(struct radv_physical_device *physical_device); @@ -366,7 +379,11 @@ struct radv_pipeline_key { uint32_t instance_rate_inputs; uint32_t instance_rate_divisors[MAX_VERTEX_ATTRIBS]; uint8_t vertex_attribute_formats[MAX_VERTEX_ATTRIBS]; + uint32_t vertex_attribute_bindings[MAX_VERTEX_ATTRIBS]; + uint32_t vertex_attribute_offsets[MAX_VERTEX_ATTRIBS]; + uint32_t vertex_attribute_strides[MAX_VERTEX_ATTRIBS]; uint64_t vertex_alpha_adjust; + uint32_t vertex_post_shuffle; unsigned tess_input_vertices; uint32_t col_format; uint32_t is_int8; @@ -392,7 +409,8 @@ bool radv_create_shader_variants_from_pipeline_cache(struct radv_device *device, struct radv_pipeline_cache *cache, const unsigned char *sha1, - struct radv_shader_variant **variants); + struct radv_shader_variant **variants, + bool *found_in_application_cache); void radv_pipeline_cache_insert_shaders(struct radv_device *device, @@ -687,9 +705,8 @@ struct radv_device { float sample_locations_2x[2][2]; float sample_locations_4x[4][2]; float sample_locations_8x[8][2]; - float sample_locations_16x[16][2]; - /* CIK and later */ + /* GFX7 and later */ uint32_t gfx_init_size_dw; struct radeon_winsys_bo *gfx_init; @@ -798,7 +815,8 @@ struct radv_descriptor_update_template_entry { uint32_t buffer_offset; /* Only valid for combined image samplers and samplers */ - uint16_t has_sampler; + uint8_t has_sampler; + uint8_t sampler_offset; /* In bytes */ size_t src_offset; @@ -838,7 +856,8 @@ enum radv_dynamic_state_bits { RADV_DYNAMIC_STENCIL_WRITE_MASK = 1 << 7, RADV_DYNAMIC_STENCIL_REFERENCE = 1 << 8, RADV_DYNAMIC_DISCARD_RECTANGLE = 1 << 9, - RADV_DYNAMIC_ALL = (1 << 10) - 1, + RADV_DYNAMIC_SAMPLE_LOCATIONS = 1 << 10, + RADV_DYNAMIC_ALL = (1 << 11) - 1, }; enum radv_cmd_dirty_bits { @@ -854,12 +873,13 @@ enum radv_cmd_dirty_bits { RADV_CMD_DIRTY_DYNAMIC_STENCIL_WRITE_MASK = 1 << 7, RADV_CMD_DIRTY_DYNAMIC_STENCIL_REFERENCE = 1 << 8, RADV_CMD_DIRTY_DYNAMIC_DISCARD_RECTANGLE = 1 << 9, - RADV_CMD_DIRTY_DYNAMIC_ALL = (1 << 10) - 1, - RADV_CMD_DIRTY_PIPELINE = 1 << 10, - RADV_CMD_DIRTY_INDEX_BUFFER = 1 << 11, - RADV_CMD_DIRTY_FRAMEBUFFER = 1 << 12, - RADV_CMD_DIRTY_VERTEX_BUFFER = 1 << 13, - RADV_CMD_DIRTY_STREAMOUT_BUFFER = 1 << 14, + RADV_CMD_DIRTY_DYNAMIC_SAMPLE_LOCATIONS = 1 << 10, + RADV_CMD_DIRTY_DYNAMIC_ALL = (1 << 11) - 1, + RADV_CMD_DIRTY_PIPELINE = 1 << 11, + RADV_CMD_DIRTY_INDEX_BUFFER = 1 << 12, + RADV_CMD_DIRTY_FRAMEBUFFER = 1 << 13, + RADV_CMD_DIRTY_VERTEX_BUFFER = 1 << 14, + RADV_CMD_DIRTY_STREAMOUT_BUFFER = 1 << 15, }; enum radv_cmd_flush_bits { @@ -936,6 +956,13 @@ struct radv_discard_rectangle_state { VkRect2D rectangles[MAX_DISCARD_RECTANGLES]; }; +struct radv_sample_locations_state { + VkSampleCountFlagBits per_pixel; + VkExtent2D grid_size; + uint32_t count; + VkSampleLocationEXT locations[MAX_SAMPLE_LOCATIONS]; +}; + struct radv_dynamic_state { /** * Bitmask of (1 << VK_DYNAMIC_STATE_*). @@ -978,6 +1005,8 @@ struct radv_dynamic_state { } stencil_reference; struct radv_discard_rectangle_state discard_rectangle; + + struct radv_sample_locations_state sample_location; }; extern const struct radv_dynamic_state default_dynamic_state; @@ -998,6 +1027,7 @@ struct radv_attachment_state { uint32_t cleared_views; VkClearValue clear_value; VkImageLayout current_layout; + struct radv_sample_locations_state sample_location; }; struct radv_descriptor_state { @@ -1009,6 +1039,11 @@ struct radv_descriptor_state { uint32_t dynamic_buffers[4 * MAX_DYNAMIC_BUFFERS]; }; +struct radv_subpass_sample_locs_state { + uint32_t subpass_idx; + struct radv_sample_locations_state sample_location; +}; + struct radv_cmd_state { /* Vertex descriptors */ uint64_t vb_va; @@ -1031,6 +1066,9 @@ struct radv_cmd_state { struct radv_streamout_state streamout; VkRect2D render_area; + uint32_t num_subpass_sample_locs; + struct radv_subpass_sample_locs_state * subpass_sample_locs; + /* Index buffer */ struct radv_buffer *index_buffer; uint64_t index_offset; @@ -1128,6 +1166,11 @@ struct radv_cmd_buffer { * Whether a query pool has been resetted and we have to flush caches. */ bool pending_reset_query; + + /** + * Bitmask of pending active query flushes. + */ + enum radv_cmd_flush_bits active_query_flush_bits; }; struct radv_image; @@ -1148,6 +1191,7 @@ void si_write_scissors(struct radeon_cmdbuf *cs, int first, const VkViewport *viewports, bool can_use_guardband); uint32_t si_get_ia_multi_vgt_param(struct radv_cmd_buffer *cmd_buffer, bool instanced_draw, bool indirect_draw, + bool count_from_stream_output, uint32_t draw_vertex_count); void si_cs_emit_write_event_eop(struct radeon_cmdbuf *cs, enum chip_class chip_class, @@ -1197,8 +1241,8 @@ void radv_cmd_buffer_clear_subpass(struct radv_cmd_buffer *cmd_buffer); void radv_cmd_buffer_resolve_subpass(struct radv_cmd_buffer *cmd_buffer); void radv_cmd_buffer_resolve_subpass_cs(struct radv_cmd_buffer *cmd_buffer); void radv_cmd_buffer_resolve_subpass_fs(struct radv_cmd_buffer *cmd_buffer); -void radv_cayman_emit_msaa_sample_locs(struct radeon_cmdbuf *cs, int nr_samples); -unsigned radv_cayman_get_maxdist(int log_samples); +void radv_emit_default_sample_locations(struct radeon_cmdbuf *cs, int nr_samples); +unsigned radv_get_default_max_sample_dist(int log_samples); void radv_device_init_msaa(struct radv_device *device); void radv_update_ds_clear_metadata(struct radv_cmd_buffer *cmd_buffer, @@ -1338,11 +1382,7 @@ struct radv_prim_vertex_count { }; struct radv_vertex_elements_info { - uint32_t rsrc_word3[MAX_VERTEX_ATTRIBS]; uint32_t format_size[MAX_VERTEX_ATTRIBS]; - uint32_t binding[MAX_VERTEX_ATTRIBS]; - uint32_t offset[MAX_VERTEX_ATTRIBS]; - uint32_t count; }; struct radv_ia_multi_vgt_param_helpers { @@ -1374,6 +1414,7 @@ struct radv_pipeline { struct radv_vertex_elements_info vertex_elements; uint32_t binding_stride[MAX_VBS]; + uint8_t num_vertex_bindings; uint32_t user_data_0[MESA_SHADER_STAGES]; union { @@ -1465,6 +1506,7 @@ bool radv_format_pack_clear_color(VkFormat format, bool radv_is_colorbuffer_format_supported(VkFormat format, bool *blendable); bool radv_dcc_formats_compatible(VkFormat format1, VkFormat format2); +bool radv_device_supports_etc(struct radv_physical_device *physical_device); struct radv_fmask_info { uint64_t offset; @@ -1484,6 +1526,13 @@ struct radv_cmask_info { unsigned slice_tile_max; }; + +struct radv_image_plane { + VkFormat format; + struct radeon_surf surface; + uint64_t offset; +}; + struct radv_image { VkImageType type; /* The original VkFormat provided by the client. This may not match any @@ -1509,7 +1558,6 @@ struct radv_image { uint64_t dcc_offset; uint64_t htile_offset; bool tc_compatible_htile; - struct radeon_surf surface; struct radv_fmask_info fmask; struct radv_cmask_info cmask; @@ -1527,6 +1575,9 @@ struct radv_image { /* For VK_ANDROID_native_buffer, the WSI image owns the memory, */ VkDeviceMemory owned_memory; + + unsigned plane_count; + struct radv_image_plane planes[0]; }; /* Whether the image has a htile that is known consistent with the contents of @@ -1577,7 +1628,7 @@ radv_image_has_fmask(const struct radv_image *image) static inline bool radv_image_has_dcc(const struct radv_image *image) { - return image->surface.dcc_size; + return image->planes[0].surface.dcc_size; } /** @@ -1587,7 +1638,7 @@ static inline bool radv_dcc_enabled(const struct radv_image *image, unsigned level) { return radv_image_has_dcc(image) && - level < image->surface.num_dcc_levels; + level < image->planes[0].surface.num_dcc_levels; } /** @@ -1607,7 +1658,7 @@ radv_image_has_CB_metadata(const struct radv_image *image) static inline bool radv_image_has_htile(const struct radv_image *image) { - return image->surface.htile_size; + return image->planes[0].surface.htile_size; } /** @@ -1652,6 +1703,21 @@ radv_init_metadata(struct radv_device *device, struct radv_image *image, struct radeon_bo_metadata *metadata); +void +radv_image_override_offset_stride(struct radv_device *device, + struct radv_image *image, + uint64_t offset, uint32_t stride); + +union radv_descriptor { + struct { + uint32_t plane0_descriptor[8]; + uint32_t fmask_descriptor[8]; + }; + struct { + uint32_t plane_descriptors[3][8]; + }; +}; + struct radv_image_view { struct radv_image *image; /**< VkImageViewCreateInfo::image */ struct radeon_winsys_bo *bo; @@ -1659,24 +1725,27 @@ struct radv_image_view { VkImageViewType type; VkImageAspectFlags aspect_mask; VkFormat vk_format; + unsigned plane_id; + bool multiple_planes; uint32_t base_layer; uint32_t layer_count; uint32_t base_mip; uint32_t level_count; VkExtent3D extent; /**< Extent of VkImageViewCreateInfo::baseMipLevel. */ - uint32_t descriptor[16]; + union radv_descriptor descriptor; /* Descriptor for use as a storage image as opposed to a sampled image. * This has a few differences for cube maps (e.g. type). */ - uint32_t storage_descriptor[16]; + union radv_descriptor storage_descriptor; }; struct radv_image_create_info { const VkImageCreateInfo *vk_info; bool scanout; bool no_metadata_planes; + const struct radeon_bo_metadata *bo_metadata; }; VkResult radv_image_create(VkDevice _device, @@ -1695,6 +1764,17 @@ void radv_image_view_init(struct radv_image_view *view, struct radv_device *device, const VkImageViewCreateInfo* pCreateInfo); +VkFormat radv_get_aspect_format(struct radv_image *image, VkImageAspectFlags mask); + +struct radv_sampler_ycbcr_conversion { + VkFormat format; + VkSamplerYcbcrModelConversion ycbcr_model; + VkSamplerYcbcrRange ycbcr_range; + VkComponentMapping components; + VkChromaLocation chroma_offsets[2]; + VkFilter chroma_filter; +}; + struct radv_buffer_view { struct radeon_winsys_bo *bo; VkFormat vk_format; @@ -1750,6 +1830,7 @@ radv_image_extent_compare(const struct radv_image *image, struct radv_sampler { uint32_t state[4]; + struct radv_sampler_ycbcr_conversion *ycbcr_sampler; }; struct radv_color_buffer_info { @@ -1757,7 +1838,6 @@ struct radv_color_buffer_info { uint64_t cb_color_cmask; uint64_t cb_color_fmask; uint64_t cb_dcc_base; - uint32_t cb_color_pitch; uint32_t cb_color_slice; uint32_t cb_color_view; uint32_t cb_color_info; @@ -1766,6 +1846,10 @@ struct radv_color_buffer_info { uint32_t cb_dcc_control; uint32_t cb_color_cmask_slice; uint32_t cb_color_fmask_slice; + union { + uint32_t cb_color_pitch; // GFX6-GFX8 + uint32_t cb_mrt_epitch; // GFX9+ + }; }; struct radv_ds_buffer_info { @@ -1849,7 +1933,8 @@ struct radv_render_pass_attachment { VkImageLayout initial_layout; VkImageLayout final_layout; - /* The subpass id in which the attachment will be used last. */ + /* The subpass id in which the attachment will be used first/last. */ + uint32_t first_subpass_idx; uint32_t last_subpass_idx; }; @@ -1919,8 +2004,6 @@ void radv_initialize_fmask(struct radv_cmd_buffer *cmd_buffer, struct radv_fence { struct radeon_winsys_fence *fence; struct wsi_fence *fence_wsi; - bool submitted; - bool signalled; uint32_t syncobj; uint32_t temp_syncobj; @@ -1959,6 +2042,8 @@ void radv_nir_shader_info_init(struct radv_shader_info *info); struct radeon_winsys_sem; +uint64_t radv_get_current_time(void); + #define RADV_DEFINE_HANDLE_CASTS(__radv_type, __VkType) \ \ static inline struct __radv_type * \ @@ -2015,6 +2100,7 @@ RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_pipeline_layout, VkPipelineLayout) RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_query_pool, VkQueryPool) RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_render_pass, VkRenderPass) RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_sampler, VkSampler) +RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_sampler_ycbcr_conversion, VkSamplerYcbcrConversion) RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_shader_module, VkShaderModule) RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_semaphore, VkSemaphore)