X-Git-Url: https://git.libre-soc.org/?a=blobdiff_plain;ds=sidebyside;f=src%2Fcpu%2Fsimple_thread.hh;h=e862385c57833cefe29dc993dcf0d3709061b490;hb=34ad1123ee5927e3b1503f07649620a533d3eab9;hp=4baf832f6420e067a5370421959f2ea12ca420f5;hpb=3595b0c5a1a3e398a7efae932cd4175cd1ca3f0e;p=gem5.git diff --git a/src/cpu/simple_thread.hh b/src/cpu/simple_thread.hh index 4baf832f6..e862385c5 100644 --- a/src/cpu/simple_thread.hh +++ b/src/cpu/simple_thread.hh @@ -1,4 +1,17 @@ /* + * Copyright (c) 2011-2012 ARM Limited + * Copyright (c) 2013 Advanced Micro Devices, Inc. + * All rights reserved + * + * The license below extends only to copyright in the software and shall + * not be construed as granting a license to any other intellectual + * property including but not limited to intellectual property relating + * to a hardware implementation of the functionality of the software + * licensed hereunder. You may use the software subject to the license + * terms below provided that you ensure that this notice is replicated + * unmodified and in its entirety in all distributions of the software, + * modified or unmodified, in source code or in binary form. + * * Copyright (c) 2001-2006 The Regents of The University of Michigan * All rights reserved. * @@ -32,48 +45,38 @@ #ifndef __CPU_SIMPLE_THREAD_HH__ #define __CPU_SIMPLE_THREAD_HH__ +#include "arch/decoder.hh" #include "arch/isa.hh" #include "arch/isa_traits.hh" #include "arch/registers.hh" #include "arch/tlb.hh" #include "arch/types.hh" #include "base/types.hh" -#include "config/full_system.hh" #include "config/the_isa.hh" -#include "cpu/decode.hh" #include "cpu/thread_context.hh" #include "cpu/thread_state.hh" +#include "debug/CCRegs.hh" #include "debug/FloatRegs.hh" #include "debug/IntRegs.hh" +#include "mem/page_table.hh" #include "mem/request.hh" #include "sim/byteswap.hh" #include "sim/eventq.hh" +#include "sim/process.hh" #include "sim/serialize.hh" +#include "sim/system.hh" class BaseCPU; - -#if FULL_SYSTEM - -#include "sim/system.hh" +class CheckerCPU; class FunctionProfile; class ProfileNode; -class FunctionalPort; -class PhysicalPort; namespace TheISA { namespace Kernel { class Statistics; - }; -}; - -#else // !FULL_SYSTEM - -#include "mem/page_table.hh" -#include "sim/process.hh" -class TranslatingPort; - -#endif // FULL_SYSTEM + } +} /** * The SimpleThread object provides a combination of the ThreadState @@ -98,6 +101,7 @@ class SimpleThread : public ThreadState typedef TheISA::MiscReg MiscReg; typedef TheISA::FloatReg FloatReg; typedef TheISA::FloatRegBits FloatRegBits; + typedef TheISA::CCReg CCReg; public: typedef ThreadContext::Status Status; @@ -107,7 +111,10 @@ class SimpleThread : public ThreadState FloatRegBits i[TheISA::NumFloatRegs]; } floatRegs; TheISA::IntReg intRegs[TheISA::NumIntRegs]; - TheISA::ISA isa; // one "instance" of the current ISA. +#ifdef ISA_HAS_CC_REGS + TheISA::CCReg ccRegs[TheISA::NumCCRegs]; +#endif + TheISA::ISA *const isa; // one "instance" of the current ISA. TheISA::PCState _pcState; @@ -117,12 +124,9 @@ class SimpleThread : public ThreadState public: std::string name() const { - return csprintf("%s.[tid:%i]", cpu->name(), tc->threadId()); + return csprintf("%s.[tid:%i]", baseCpu->name(), tc->threadId()); } - // pointer to CPU associated with this SimpleThread - BaseCPU *cpu; - ProxyThreadContext *tc; System *system; @@ -130,19 +134,17 @@ class SimpleThread : public ThreadState TheISA::TLB *itb; TheISA::TLB *dtb; - Decoder decoder; + TheISA::Decoder decoder; // constructor: initialize SimpleThread from given process structure -#if FULL_SYSTEM + // FS SimpleThread(BaseCPU *_cpu, int _thread_num, System *_system, - TheISA::TLB *_itb, TheISA::TLB *_dtb, + TheISA::TLB *_itb, TheISA::TLB *_dtb, TheISA::ISA *_isa, bool use_kernel_stats = true); -#else - SimpleThread(BaseCPU *_cpu, int _thread_num, Process *_process, - TheISA::TLB *_itb, TheISA::TLB *_dtb); -#endif - - SimpleThread(); + // SE + SimpleThread(BaseCPU *_cpu, int _thread_num, System *_system, + Process *_process, TheISA::TLB *_itb, TheISA::TLB *_dtb, + TheISA::ISA *_isa); virtual ~SimpleThread(); @@ -150,12 +152,11 @@ class SimpleThread : public ThreadState void regStats(const std::string &name); - void copyTC(ThreadContext *context); - void copyState(ThreadContext *oldContext); void serialize(std::ostream &os); void unserialize(Checkpoint *cp, const std::string §ion); + void startup(); /*************************************************************** * SimpleThread functions to provide CPU with access to various @@ -184,44 +185,34 @@ class SimpleThread : public ThreadState dtb->demapPage(vaddr, asn); } -#if FULL_SYSTEM void dumpFuncProfile(); Fault hwrei(); bool simPalCheck(int palFunc); -#endif - /******************************************* * ThreadContext interface functions. ******************************************/ - BaseCPU *getCpuPtr() { return cpu; } + BaseCPU *getCpuPtr() { return baseCpu; } TheISA::TLB *getITBPtr() { return itb; } TheISA::TLB *getDTBPtr() { return dtb; } - Decoder *getDecoderPtr() { return &decoder; } + CheckerCPU *getCheckerCpuPtr() { return NULL; } - System *getSystemPtr() { return system; } + TheISA::Decoder *getDecoderPtr() { return &decoder; } - FunctionalPort *getPhysPort() { return physPort; } - - /** Return a virtual port. This port cannot be cached locally in an object. - * After a CPU switch it may point to the wrong memory object which could - * mean stale data. - */ - VirtualPort *getVirtPort() { return virtPort; } + System *getSystemPtr() { return system; } Status status() const { return _status; } void setStatus(Status newStatus) { _status = newStatus; } - /// Set the status to Active. Optional delay indicates number of - /// cycles to wait before beginning execution. - void activate(int delay = 1); + /// Set the status to Active. + void activate(); /// Set the status to Suspended. void suspend(); @@ -229,8 +220,6 @@ class SimpleThread : public ThreadState /// Set the status to Halted. void halt(); - virtual bool misspeculating(); - void copyArchRegs(ThreadContext *tc); void clearArchRegs() @@ -238,7 +227,10 @@ class SimpleThread : public ThreadState _pcState = 0; memset(intRegs, 0, sizeof(intRegs)); memset(floatRegs.i, 0, sizeof(floatRegs.i)); - isa.clear(); +#ifdef ISA_HAS_CC_REGS + memset(ccRegs, 0, sizeof(ccRegs)); +#endif + isa->clear(); } // @@ -246,9 +238,9 @@ class SimpleThread : public ThreadState // uint64_t readIntReg(int reg_idx) { - int flatIndex = isa.flattenIntIndex(reg_idx); + int flatIndex = isa->flattenIntIndex(reg_idx); assert(flatIndex < TheISA::NumIntRegs); - uint64_t regVal = intRegs[flatIndex]; + uint64_t regVal(readIntRegFlat(flatIndex)); DPRINTF(IntRegs, "Reading int reg %d (%d) as %#x.\n", reg_idx, flatIndex, regVal); return regVal; @@ -256,9 +248,9 @@ class SimpleThread : public ThreadState FloatReg readFloatReg(int reg_idx) { - int flatIndex = isa.flattenFloatIndex(reg_idx); + int flatIndex = isa->flattenFloatIndex(reg_idx); assert(flatIndex < TheISA::NumFloatRegs); - FloatReg regVal = floatRegs.f[flatIndex]; + FloatReg regVal(readFloatRegFlat(flatIndex)); DPRINTF(FloatRegs, "Reading float reg %d (%d) as %f, %#x.\n", reg_idx, flatIndex, regVal, floatRegs.i[flatIndex]); return regVal; @@ -266,41 +258,73 @@ class SimpleThread : public ThreadState FloatRegBits readFloatRegBits(int reg_idx) { - int flatIndex = isa.flattenFloatIndex(reg_idx); + int flatIndex = isa->flattenFloatIndex(reg_idx); assert(flatIndex < TheISA::NumFloatRegs); - FloatRegBits regVal = floatRegs.i[flatIndex]; + FloatRegBits regVal(readFloatRegBitsFlat(flatIndex)); DPRINTF(FloatRegs, "Reading float reg %d (%d) bits as %#x, %f.\n", reg_idx, flatIndex, regVal, floatRegs.f[flatIndex]); return regVal; } + CCReg readCCReg(int reg_idx) + { +#ifdef ISA_HAS_CC_REGS + int flatIndex = isa->flattenCCIndex(reg_idx); + assert(0 <= flatIndex); + assert(flatIndex < TheISA::NumCCRegs); + uint64_t regVal(readCCRegFlat(flatIndex)); + DPRINTF(CCRegs, "Reading CC reg %d (%d) as %#x.\n", + reg_idx, flatIndex, regVal); + return regVal; +#else + panic("Tried to read a CC register."); + return 0; +#endif + } + void setIntReg(int reg_idx, uint64_t val) { - int flatIndex = isa.flattenIntIndex(reg_idx); + int flatIndex = isa->flattenIntIndex(reg_idx); assert(flatIndex < TheISA::NumIntRegs); DPRINTF(IntRegs, "Setting int reg %d (%d) to %#x.\n", reg_idx, flatIndex, val); - intRegs[flatIndex] = val; + setIntRegFlat(flatIndex, val); } void setFloatReg(int reg_idx, FloatReg val) { - int flatIndex = isa.flattenFloatIndex(reg_idx); + int flatIndex = isa->flattenFloatIndex(reg_idx); assert(flatIndex < TheISA::NumFloatRegs); - floatRegs.f[flatIndex] = val; + setFloatRegFlat(flatIndex, val); DPRINTF(FloatRegs, "Setting float reg %d (%d) to %f, %#x.\n", reg_idx, flatIndex, val, floatRegs.i[flatIndex]); } void setFloatRegBits(int reg_idx, FloatRegBits val) { - int flatIndex = isa.flattenFloatIndex(reg_idx); + int flatIndex = isa->flattenFloatIndex(reg_idx); assert(flatIndex < TheISA::NumFloatRegs); - floatRegs.i[flatIndex] = val; + // XXX: Fix array out of bounds compiler error for gem5.fast + // when checkercpu enabled + if (flatIndex < TheISA::NumFloatRegs) + setFloatRegBitsFlat(flatIndex, val); DPRINTF(FloatRegs, "Setting float reg %d (%d) bits to %#x, %#f.\n", reg_idx, flatIndex, val, floatRegs.f[flatIndex]); } + void setCCReg(int reg_idx, CCReg val) + { +#ifdef ISA_HAS_CC_REGS + int flatIndex = isa->flattenCCIndex(reg_idx); + assert(flatIndex < TheISA::NumCCRegs); + DPRINTF(CCRegs, "Setting CC reg %d (%d) to %#x.\n", + reg_idx, flatIndex, val); + setCCRegFlat(flatIndex, val); +#else + panic("Tried to set a CC register."); +#endif + } + TheISA::PCState pcState() { @@ -313,6 +337,12 @@ class SimpleThread : public ThreadState _pcState = val; } + void + pcStateNoRecord(const TheISA::PCState &val) + { + _pcState = val; + } + Addr instAddr() { @@ -342,39 +372,51 @@ class SimpleThread : public ThreadState } MiscReg - readMiscRegNoEffect(int misc_reg, ThreadID tid = 0) + readMiscRegNoEffect(int misc_reg, ThreadID tid = 0) const { - return isa.readMiscRegNoEffect(misc_reg); + return isa->readMiscRegNoEffect(misc_reg); } MiscReg readMiscReg(int misc_reg, ThreadID tid = 0) { - return isa.readMiscReg(misc_reg, tc); + return isa->readMiscReg(misc_reg, tc); } void setMiscRegNoEffect(int misc_reg, const MiscReg &val, ThreadID tid = 0) { - return isa.setMiscRegNoEffect(misc_reg, val); + return isa->setMiscRegNoEffect(misc_reg, val); } void setMiscReg(int misc_reg, const MiscReg &val, ThreadID tid = 0) { - return isa.setMiscReg(misc_reg, val, tc); + return isa->setMiscReg(misc_reg, val, tc); } int flattenIntIndex(int reg) { - return isa.flattenIntIndex(reg); + return isa->flattenIntIndex(reg); } int flattenFloatIndex(int reg) { - return isa.flattenFloatIndex(reg); + return isa->flattenFloatIndex(reg); + } + + int + flattenCCIndex(int reg) + { + return isa->flattenCCIndex(reg); + } + + int + flattenMiscIndex(int reg) + { + return isa->flattenMiscIndex(reg); } unsigned readStCondFailures() { return storeCondFailures; } @@ -382,20 +424,33 @@ class SimpleThread : public ThreadState void setStCondFailures(unsigned sc_failures) { storeCondFailures = sc_failures; } -#if !FULL_SYSTEM void syscall(int64_t callnum) { process->syscall(callnum, tc); } + + uint64_t readIntRegFlat(int idx) { return intRegs[idx]; } + void setIntRegFlat(int idx, uint64_t val) { intRegs[idx] = val; } + + FloatReg readFloatRegFlat(int idx) { return floatRegs.f[idx]; } + void setFloatRegFlat(int idx, FloatReg val) { floatRegs.f[idx] = val; } + + FloatRegBits readFloatRegBitsFlat(int idx) { return floatRegs.i[idx]; } + void setFloatRegBitsFlat(int idx, FloatRegBits val) { + floatRegs.i[idx] = val; + } + +#ifdef ISA_HAS_CC_REGS + CCReg readCCRegFlat(int idx) { return ccRegs[idx]; } + void setCCRegFlat(int idx, CCReg val) { ccRegs[idx] = val; } +#else + CCReg readCCRegFlat(int idx) + { panic("readCCRegFlat w/no CC regs!\n"); } + + void setCCRegFlat(int idx, CCReg val) + { panic("setCCRegFlat w/no CC regs!\n"); } #endif }; -// for non-speculative execution context, spec_mode is always false -inline bool -SimpleThread::misspeculating() -{ - return false; -} - #endif // __CPU_CPU_EXEC_CONTEXT_HH__