X-Git-Url: https://git.libre-soc.org/?a=blobdiff_plain;ds=sidebyside;f=src%2Fgallium%2Fdrivers%2Fetnaviv%2Fetnaviv_internal.h;h=c5b2dc14b1a04f996a7af9861bb4632b7f859a75;hb=7cdde962c5f65165e28cae92da57d2d6e4d7a740;hp=fa75c3e936c7f831258fe5eb5ea81ee22fc249b5;hpb=c9e8b49b885242d84ba031dacef5aa4a5ac1e5b6;p=mesa.git diff --git a/src/gallium/drivers/etnaviv/etnaviv_internal.h b/src/gallium/drivers/etnaviv/etnaviv_internal.h index fa75c3e936c..c5b2dc14b1a 100644 --- a/src/gallium/drivers/etnaviv/etnaviv_internal.h +++ b/src/gallium/drivers/etnaviv/etnaviv_internal.h @@ -31,7 +31,7 @@ #include "hw/state.xml.h" #include "hw/state_3d.xml.h" -#include +#include "drm/etnaviv_drmif.h" #define ETNA_NUM_INPUTS (16) #define ETNA_NUM_VARYINGS 8 @@ -47,8 +47,21 @@ /* PE render targets must be aligned to 64 bytes */ #define ETNA_PE_ALIGNMENT (64) +/* These demarcate the margin (fixp16) between the computed sizes and the + value sent to the chip. These have been set to the numbers used by the + Vivante driver on gc2000. They used to be -1 for scissor right and bottom. I + am not sure whether older hardware was relying on these or they were just a + guess. But if so, these need to be moved to the _specs structure. +*/ +#define ETNA_SE_SCISSOR_MARGIN_RIGHT (0x1119) +#define ETNA_SE_SCISSOR_MARGIN_BOTTOM (0x1111) +#define ETNA_SE_CLIP_MARGIN_RIGHT (0xffff) +#define ETNA_SE_CLIP_MARGIN_BOTTOM (0xffff) + /* GPU chip 3D specs */ struct etna_specs { + /* HALTI (gross architecture) level. -1 for pre-HALTI. */ + int halti : 8; /* supports SUPERTILE (64x64) tiling? */ unsigned can_supertile : 1; /* needs z=(z+w)/2, for older GCxxx */ @@ -59,8 +72,24 @@ struct etna_specs { unsigned has_sign_floor_ceil : 1; /* can use VS_RANGE, PS_RANGE registers*/ unsigned has_shader_range_registers : 1; + /* has the new sin/cos/log functions */ + unsigned has_new_transcendentals : 1; + /* has the new dp2/dpX_norm instructions, among others */ + unsigned has_halti2_instructions : 1; + /* has V4_COMPRESSION */ + unsigned v4_compression : 1; + /* supports single-buffer rendering with multiple pixel pipes */ + unsigned single_buffer : 1; + /* has unified uniforms memory */ + unsigned has_unified_uniforms : 1; + /* can load shader instructions from memory */ + unsigned has_icache : 1; + /* ASTC texture support (and has associated states) */ + unsigned tex_astc : 1; + /* has BLT engine instead of RS */ + unsigned use_blt : 1; /* can use any kind of wrapping mode on npot textures */ - unsigned npot_tex_any_wrap; + unsigned npot_tex_any_wrap : 1; /* number of bits per TS tile */ unsigned bits_per_tile; /* clear value for TS (dependent on bits_per_tile) */ @@ -85,6 +114,10 @@ struct etna_specs { uint32_t vs_offset; /* pixel shader memory address*/ uint32_t ps_offset; + /* vertex shader uniforms address*/ + uint32_t vs_uniforms_offset; + /* pixel shader uniforms address*/ + uint32_t ps_uniforms_offset; /* vertex/fragment shader max instructions */ uint32_t max_instructions; /* maximum number of varyings */ @@ -111,7 +144,10 @@ struct etna_specs { /* Compiled pipe_blend_color */ struct compiled_blend_color { + float color[4]; uint32_t PE_ALPHA_BLEND_COLOR; + uint32_t PE_ALPHA_COLOR_EXT0; + uint32_t PE_ALPHA_COLOR_EXT1; }; /* Compiled pipe_stencil_ref */ @@ -126,6 +162,8 @@ struct compiled_scissor_state { uint32_t SE_SCISSOR_TOP; uint32_t SE_SCISSOR_RIGHT; uint32_t SE_SCISSOR_BOTTOM; + uint32_t SE_CLIP_RIGHT; + uint32_t SE_CLIP_BOTTOM; }; /* Compiled pipe_viewport_state */ @@ -140,13 +178,14 @@ struct compiled_viewport_state { uint32_t SE_SCISSOR_TOP; uint32_t SE_SCISSOR_RIGHT; uint32_t SE_SCISSOR_BOTTOM; + uint32_t SE_CLIP_RIGHT; + uint32_t SE_CLIP_BOTTOM; uint32_t PE_DEPTH_NEAR; uint32_t PE_DEPTH_FAR; }; /* Compiled pipe_framebuffer_state */ struct compiled_framebuffer_state { - struct pipe_surface *cbuf, *zsbuf; /* keep reference to surfaces */ uint32_t GL_MULTI_SAMPLE_CONFIG; uint32_t PE_COLOR_FORMAT; uint32_t PE_DEPTH_CONFIG; @@ -158,10 +197,13 @@ struct compiled_framebuffer_state { struct etna_reloc PE_COLOR_ADDR; struct etna_reloc PE_PIPE_COLOR_ADDR[ETNA_MAX_PIXELPIPES]; uint32_t PE_COLOR_STRIDE; + uint32_t PE_MEM_CONFIG; uint32_t SE_SCISSOR_LEFT; uint32_t SE_SCISSOR_TOP; uint32_t SE_SCISSOR_RIGHT; uint32_t SE_SCISSOR_BOTTOM; + uint32_t SE_CLIP_RIGHT; + uint32_t SE_CLIP_BOTTOM; uint32_t RA_MULTISAMPLE_UNK00E04; uint32_t RA_MULTISAMPLE_UNK00E10[VIVS_RA_MULTISAMPLE_UNK00E10__LEN]; uint32_t RA_CENTROID_TABLE[VIVS_RA_CENTROID_TABLE__LEN]; @@ -172,6 +214,7 @@ struct compiled_framebuffer_state { uint32_t TS_COLOR_CLEAR_VALUE; struct etna_reloc TS_COLOR_STATUS_BASE; struct etna_reloc TS_COLOR_SURFACE_BASE; + uint32_t PE_LOGIC_OP; bool msaa_mode; /* adds input (and possible temp) to PS */ }; @@ -179,11 +222,15 @@ struct compiled_framebuffer_state { struct compiled_vertex_elements_state { unsigned num_elements; uint32_t FE_VERTEX_ELEMENT_CONFIG[VIVS_FE_VERTEX_ELEMENT_CONFIG__LEN]; + uint32_t NFE_GENERIC_ATTRIB_CONFIG0[VIVS_NFE_GENERIC_ATTRIB__LEN]; + uint32_t NFE_GENERIC_ATTRIB_SCALE[VIVS_NFE_GENERIC_ATTRIB__LEN]; + uint32_t NFE_GENERIC_ATTRIB_CONFIG1[VIVS_NFE_GENERIC_ATTRIB__LEN]; }; /* Compiled context->set_vertex_buffer result */ struct compiled_set_vertex_buffer { uint32_t FE_VERTEX_STREAM_CONTROL; + uint32_t FE_VERTEX_STREAM_UNK14680; struct etna_reloc FE_VERTEX_STREAM_BASE_ADDR; }; @@ -213,6 +260,7 @@ struct compiled_shader_state { uint32_t GL_VARYING_TOTAL_COMPONENTS; uint32_t GL_VARYING_NUM_COMPONENTS; uint32_t GL_VARYING_COMPONENT_USE[2]; + uint32_t GL_HALTI5_SH_SPECIALS; unsigned vs_inst_mem_size; unsigned vs_uniforms_size; unsigned ps_inst_mem_size; @@ -221,16 +269,12 @@ struct compiled_shader_state { uint32_t VS_UNIFORMS[ETNA_MAX_UNIFORMS * 4]; uint32_t *PS_INST_MEM; uint32_t PS_UNIFORMS[ETNA_MAX_UNIFORMS * 4]; + struct etna_reloc PS_INST_ADDR; + struct etna_reloc VS_INST_ADDR; }; /* state of some 3d and common registers relevant to etna driver */ struct etna_3d_state { - unsigned vs_uniforms_size; - unsigned ps_uniforms_size; - - uint32_t /*01008*/ PS_INPUT_COUNT; - uint32_t /*0100C*/ PS_TEMP_REGISTER_CONTROL; - uint32_t /*03818*/ GL_MULTI_SAMPLE_CONFIG; uint32_t /*05000*/ VS_UNIFORMS[VIVS_VS_UNIFORMS__LEN]; uint32_t /*07000*/ PS_UNIFORMS[VIVS_PS_UNIFORMS__LEN]; };