X-Git-Url: https://git.libre-soc.org/?a=blobdiff_plain;ds=sidebyside;f=src%2Fgallium%2Fdrivers%2Fsoftpipe%2Fsp_tile_cache.h;h=68140b1d2f9f0965304feec0d90825c7ee6200af;hb=88349255ce19b894e98fdf63a47c8219e601798f;hp=753d8c0daac89fce8278d142df7b5d0ec9ad9327;hpb=8f3bdeaad610d7d5a5c6e73e1e9c721219595754;p=mesa.git diff --git a/src/gallium/drivers/softpipe/sp_tile_cache.h b/src/gallium/drivers/softpipe/sp_tile_cache.h index 753d8c0daac..68140b1d2f9 100644 --- a/src/gallium/drivers/softpipe/sp_tile_cache.h +++ b/src/gallium/drivers/softpipe/sp_tile_cache.h @@ -28,10 +28,9 @@ #ifndef SP_TILE_CACHE_H #define SP_TILE_CACHE_H -#define TILE_CLEAR_OPTIMIZATION 1 - #include "pipe/p_compiler.h" +#include "sp_texture.h" struct softpipe_tile_cache; @@ -40,18 +39,22 @@ struct softpipe_tile_cache; /** * Cache tile size (width and height). This needs to be a power of two. */ -#define TILE_SIZE 64 +#define TILE_SIZE_LOG2 6 +#define TILE_SIZE (1 << TILE_SIZE_LOG2) + +#define TILE_ADDR_BITS (SP_MAX_TEXTURE_2D_LEVELS - 1 - TILE_SIZE_LOG2) -/* If we need to support > 4096, just expand this to be a 64 bit - * union, or consider tiling in Z as well. + +/** + * Surface tile address as a union for fast compares. */ union tile_address { struct { - unsigned x:6; /* 4096 / TILE_SIZE */ - unsigned y:6; /* 4096 / TILE_SIZE */ + unsigned x:TILE_ADDR_BITS; /* 16K / TILE_SIZE */ + unsigned y:TILE_ADDR_BITS; /* 16K / TILE_SIZE */ unsigned invalid:1; - unsigned pad:19; + unsigned pad:15; } bits; unsigned value; }; @@ -59,7 +62,6 @@ union tile_address { struct softpipe_cached_tile { - union tile_address addr; union { float color[TILE_SIZE][TILE_SIZE][4]; uint color32[TILE_SIZE][TILE_SIZE]; @@ -73,11 +75,6 @@ struct softpipe_cached_tile #define NUM_ENTRIES 50 -/** XXX move these */ -#define MAX_WIDTH 4096 -#define MAX_HEIGHT 4096 - - struct softpipe_tile_cache { struct pipe_context *pipe; @@ -85,14 +82,16 @@ struct softpipe_tile_cache struct pipe_transfer *transfer; void *transfer_map; - struct softpipe_cached_tile entries[NUM_ENTRIES]; + union tile_address tile_addrs[NUM_ENTRIES]; + struct softpipe_cached_tile *entries[NUM_ENTRIES]; uint clear_flags[(MAX_WIDTH / TILE_SIZE) * (MAX_HEIGHT / TILE_SIZE) / 32]; float clear_color[4]; /**< for color bufs */ - uint clear_val; /**< for z+stencil, or packed color clear value */ + uint clear_val; /**< for z+stencil */ boolean depth_stencil; /**< Is the surface a depth/stencil format? */ - struct softpipe_cached_tile tile; /**< scratch tile for clears */ + struct softpipe_cached_tile *tile; /**< scratch tile for clears */ + union tile_address last_tile_addr; struct softpipe_cached_tile *last_tile; /**< most recently retrieved tile */ }; @@ -149,7 +148,7 @@ sp_get_cached_tile(struct softpipe_tile_cache *tc, { union tile_address addr = tile_address( x, y ); - if (tc->last_tile->addr.value == addr.value) + if (tc->last_tile_addr.value == addr.value) return tc->last_tile; return sp_find_cached_tile( tc, addr );