X-Git-Url: https://git.libre-soc.org/?a=blobdiff_plain;ds=sidebyside;f=src%2Fieee754%2Ffpadd%2Fspecialcases.py;h=656ace3ceced434ee50a16740bd299db8e5bc8ec;hb=493bdd9752ad3f296ccbf48c2eeeffda8a6875e8;hp=d6dea0ac4950e34a3094571d9f282260e653590b;hpb=f09f35af37956dc1e3cc01aadc84ad07a711d2d4;p=ieee754fpu.git diff --git a/src/ieee754/fpadd/specialcases.py b/src/ieee754/fpadd/specialcases.py index d6dea0ac..656ace3c 100644 --- a/src/ieee754/fpadd/specialcases.py +++ b/src/ieee754/fpadd/specialcases.py @@ -2,222 +2,134 @@ # Copyright (C) Jonathan P Dawson 2013 # 2013-12-12 -from nmigen import Module, Signal, Cat, Const +from nmigen import Module, Signal, Cat, Const, Mux from nmigen.cli import main, verilog from math import log +from nmutil.pipemodbase import PipeModBase, PipeModBaseChain from ieee754.fpcommon.fpbase import FPNumDecode -from nmutil.singlepipe import SimpleHandshake, StageChain -from ieee754.fpcommon.fpbase import FPState, FPID -from ieee754.fpcommon.getop import FPADDBaseData +from ieee754.fpcommon.fpbase import FPNumBaseRecord +from ieee754.fpcommon.basedata import FPBaseData from ieee754.fpcommon.denorm import (FPSCData, FPAddDeNormMod) -class FPAddSpecialCasesMod: +class FPAddSpecialCasesMod(PipeModBase): """ special cases: NaNs, infs, zeros, denormalised NOTE: some of these are unique to add. see "Special Operations" https://steve.hollasch.net/cgindex/coding/ieeefloat.html """ - def __init__(self, width, id_wid): - self.width = width - self.id_wid = id_wid - self.i = self.ispec() - self.o = self.ospec() + def __init__(self, pspec): + super().__init__(pspec, "specialcases") def ispec(self): - return FPADDBaseData(self.width, self.id_wid) + return FPBaseData(self.pspec) def ospec(self): - return FPSCData(self.width, self.id_wid) - - def setup(self, m, i): - """ links module to inputs and outputs - """ - m.submodules.specialcases = self - m.d.comb += self.i.eq(i) - - def process(self, i): - return self.o + return FPSCData(self.pspec, True) def elaborate(self, platform): m = Module() - - m.submodules.sc_out_z = self.o.z + comb = m.d.comb # decode: XXX really should move to separate stage - a1 = FPNumDecode(None, self.width) - b1 = FPNumDecode(None, self.width) - m.submodules.sc_decode_a = a1 - m.submodules.sc_decode_b = b1 - m.d.comb += [a1.v.eq(self.i.a), + width = self.pspec.width + a1 = FPNumBaseRecord(width) + b1 = FPNumBaseRecord(width) + m.submodules.sc_decode_a = a1 = FPNumDecode(None, a1) + m.submodules.sc_decode_b = b1 = FPNumDecode(None, b1) + comb += [a1.v.eq(self.i.a), b1.v.eq(self.i.b), self.o.a.eq(a1), self.o.b.eq(b1) ] + # temporaries used below s_nomatch = Signal(reset_less=True) - m.d.comb += s_nomatch.eq(a1.s != b1.s) - m_match = Signal(reset_less=True) - m.d.comb += m_match.eq(a1.m == b1.m) - e_match = Signal(reset_less=True) - m.d.comb += e_match.eq(a1.e == b1.e) - - aeqmb = Signal(reset_less=True) - m.d.comb += aeqmb.eq(s_nomatch & m_match & e_match) - - abz = Signal(reset_less=True) - m.d.comb += abz.eq(a1.is_zero & b1.is_zero) - - abnan = Signal(reset_less=True) - m.d.comb += abnan.eq(a1.is_nan | b1.is_nan) - + absa = Signal(reset_less=True) # a1.s & b1.s + t_aeqmb = Signal(reset_less=True) + t_a1inf = Signal(reset_less=True) + t_b1inf = Signal(reset_less=True) + t_a1zero = Signal(reset_less=True) + t_b1zero = Signal(reset_less=True) + t_abz = Signal(reset_less=True) + t_abnan = Signal(reset_less=True) bexp128s = Signal(reset_less=True) - m.d.comb += bexp128s.eq(b1.exp_128 & s_nomatch) - + t_special = Signal(reset_less=True) + + comb += s_nomatch.eq(a1.s != b1.s) + comb += m_match.eq(a1.m == b1.m) + comb += e_match.eq(a1.e == b1.e) + + # logic-chain (matches comments, below) gives an if-elif-elif-elif... + comb += t_abnan.eq(a1.is_nan | b1.is_nan) + comb += t_a1inf.eq(a1.is_inf) + comb += t_b1inf.eq(b1.is_inf) + comb += t_abz.eq(a1.is_zero & b1.is_zero) + comb += t_a1zero.eq(a1.is_zero) + comb += t_b1zero.eq(b1.is_zero) + comb += t_aeqmb.eq(s_nomatch & m_match & e_match) + comb += t_special.eq(Cat(t_aeqmb, t_b1zero, t_a1zero, t_abz, + t_b1inf, t_a1inf, t_abnan).bool()) + + comb += absa.eq(a1.s & b1.s) + comb += bexp128s.eq(b1.exp_128 & s_nomatch) + + # prepare inf/zero/nans + z_zero = FPNumBaseRecord(width, False, name="z_zero") + z_nan = FPNumBaseRecord(width, False, name="z_nan") + z_infa = FPNumBaseRecord(width, False, name="z_infa") + z_infb = FPNumBaseRecord(width, False, name="z_infb") + comb += z_zero.zero(0) + comb += z_nan.nan(0) + comb += z_infa.inf(a1.s) + comb += z_infb.inf(b1.s) + + # any special-cases it's a "special". + comb += self.o.out_do_z.eq(t_special) + + # this is the logic-decision-making for special-cases: # if a is NaN or b is NaN return NaN - with m.If(abnan): - m.d.comb += self.o.out_do_z.eq(1) - m.d.comb += self.o.z.nan(0) - - # XXX WEIRDNESS for FP16 non-canonical NaN handling - # under review - - ## if a is zero and b is NaN return -b - #with m.If(a.is_zero & (a.s==0) & b.is_nan): - # m.d.comb += self.o.out_do_z.eq(1) - # m.d.comb += z.create(b.s, b.e, Cat(b.m[3:-2], ~b.m[0])) - - ## if b is zero and a is NaN return -a - #with m.Elif(b.is_zero & (b.s==0) & a.is_nan): - # m.d.comb += self.o.out_do_z.eq(1) - # m.d.comb += z.create(a.s, a.e, Cat(a.m[3:-2], ~a.m[0])) - - ## if a is -zero and b is NaN return -b - #with m.Elif(a.is_zero & (a.s==1) & b.is_nan): - # m.d.comb += self.o.out_do_z.eq(1) - # m.d.comb += z.create(a.s & b.s, b.e, Cat(b.m[3:-2], 1)) - - ## if b is -zero and a is NaN return -a - #with m.Elif(b.is_zero & (b.s==1) & a.is_nan): - # m.d.comb += self.o.out_do_z.eq(1) - # m.d.comb += z.create(a.s & b.s, a.e, Cat(a.m[3:-2], 1)) - - # if a is inf return inf (or NaN) - with m.Elif(a1.is_inf): - m.d.comb += self.o.out_do_z.eq(1) - m.d.comb += self.o.z.inf(a1.s) - # if a is inf and signs don't match return NaN - with m.If(bexp128s): - m.d.comb += self.o.z.nan(0) - - # if b is inf return inf - with m.Elif(b1.is_inf): - m.d.comb += self.o.out_do_z.eq(1) - m.d.comb += self.o.z.inf(b1.s) - - # if a is zero and b zero return signed-a/b - with m.Elif(abz): - m.d.comb += self.o.out_do_z.eq(1) - m.d.comb += self.o.z.create(a1.s & b1.s, b1.e, b1.m[3:-1]) - - # if a is zero return b - with m.Elif(a1.is_zero): - m.d.comb += self.o.out_do_z.eq(1) - m.d.comb += self.o.z.create(b1.s, b1.e, b1.m[3:-1]) - - # if b is zero return a - with m.Elif(b1.is_zero): - m.d.comb += self.o.out_do_z.eq(1) - m.d.comb += self.o.z.create(a1.s, a1.e, a1.m[3:-1]) - - # if a equal to -b return zero (+ve zero) - with m.Elif(aeqmb): - m.d.comb += self.o.out_do_z.eq(1) - m.d.comb += self.o.z.zero(0) - - # Denormalised Number checks next, so pass a/b data through - with m.Else(): - m.d.comb += self.o.out_do_z.eq(0) - - m.d.comb += self.o.oz.eq(self.o.z.v) - m.d.comb += self.o.mid.eq(self.i.mid) + # elif a is inf return inf (or NaN) + # if a is inf and signs don't match return NaN + # else return inf(a) + # elif b is inf return inf(b) + # elif a is zero and b zero return signed-a/b + # elif a is zero return b + # elif b is zero return a + # elif a equal to -b return zero (+ve zero) + + # XXX *sigh* there are better ways to do this... + # one of them: use a priority-picker! + # in reverse-order, accumulate Muxing + + oz = 0 + oz = Mux(t_aeqmb, z_zero.v, oz) + oz = Mux(t_b1zero, a1.v, oz) + oz = Mux(t_a1zero, b1.v, oz) + oz = Mux(t_abz, Cat(self.i.b[:-1], absa), oz) + oz = Mux(t_b1inf, z_infb.v, oz) + oz = Mux(t_a1inf, Mux(bexp128s, z_nan.v, z_infa.v), oz) + oz = Mux(t_abnan, z_nan.v, oz) + + comb += self.o.oz.eq(oz) + + comb += self.o.ctx.eq(self.i.ctx) return m -class FPAddSpecialCases(FPState): - """ special cases: NaNs, infs, zeros, denormalised - NOTE: some of these are unique to add. see "Special Operations" - https://steve.hollasch.net/cgindex/coding/ieeefloat.html +class FPAddSpecialCasesDeNorm(PipeModBaseChain): + """ special cases chain """ - def __init__(self, width, id_wid): - FPState.__init__(self, "special_cases") - self.mod = FPAddSpecialCasesMod(width) - self.out_z = self.mod.ospec() - self.out_do_z = Signal(reset_less=True) - - def setup(self, m, i): + def get_chain(self): """ links module to inputs and outputs """ - self.mod.setup(m, i, self.out_do_z) - m.d.sync += self.out_z.v.eq(self.mod.out_z.v) # only take the output - m.d.sync += self.out_z.mid.eq(self.mod.o.mid) # (and mid) - - def action(self, m): - self.idsync(m) - with m.If(self.out_do_z): - m.next = "put_z" - with m.Else(): - m.next = "denormalise" - - -class FPAddSpecialCasesDeNorm(FPState, SimpleHandshake): - """ special cases: NaNs, infs, zeros, denormalised - NOTE: some of these are unique to add. see "Special Operations" - https://steve.hollasch.net/cgindex/coding/ieeefloat.html - """ - - def __init__(self, width, id_wid): - FPState.__init__(self, "special_cases") - self.width = width - self.id_wid = id_wid - SimpleHandshake.__init__(self, self) # pipe is its own stage - self.out = self.ospec() - - def ispec(self): - return FPADDBaseData(self.width, self.id_wid) # SpecialCases ispec - - def ospec(self): - return FPSCData(self.width, self.id_wid) # DeNorm ospec - - def setup(self, m, i): - """ links module to inputs and outputs - """ - smod = FPAddSpecialCasesMod(self.width, self.id_wid) - dmod = FPAddDeNormMod(self.width, self.id_wid) - - chain = StageChain([smod, dmod]) - chain.setup(m, i) - - # only needed for break-out (early-out) - # self.out_do_z = smod.o.out_do_z - - self.o = dmod.o - - def process(self, i): - return self.o - - def action(self, m): - # for break-out (early-out) - #with m.If(self.out_do_z): - # m.next = "put_z" - #with m.Else(): - m.d.sync += self.out.eq(self.process(None)) - m.next = "align" - + smod = FPAddSpecialCasesMod(self.pspec) + dmod = FPAddDeNormMod(self.pspec, True) + return [smod, dmod]