X-Git-Url: https://git.libre-soc.org/?a=blobdiff_plain;ds=sidebyside;f=src%2Fmain%2Fscala%2Fdevices%2Fgpio%2FGPIO.scala;h=4a0b3fcaf8e728dfe5b40bfb1a9d5fe3faab8edf;hb=45c491cd69b3dad347d88fdec3484d51814ee243;hp=73ba3d0d6564cdcb506c15e18da0d42e2a6486e8;hpb=1443834186bad8981ed29801d3703c05218ce6dc;p=sifive-blocks.git

diff --git a/src/main/scala/devices/gpio/GPIO.scala b/src/main/scala/devices/gpio/GPIO.scala
index 73ba3d0..4a0b3fc 100644
--- a/src/main/scala/devices/gpio/GPIO.scala
+++ b/src/main/scala/devices/gpio/GPIO.scala
@@ -11,9 +11,9 @@ import util.AsyncResetRegVec
 case class GPIOConfig(address: BigInt, width: Int)
 
 trait HasGPIOParameters {
-  val params: Tuple2[Parameters, GPIOConfig]
-  implicit val p = params._1
-  val c = params._2
+  implicit val p: Parameters
+  val params: GPIOConfig
+  val c = params
 }
 
 // YAGNI: Make the PUE, DS, and
@@ -289,7 +289,7 @@ object GPIOInputPinCtrl {
 }
 
 // Magic TL2 Incantation to create a TL2 Slave
-class TLGPIO(p: Parameters, c: GPIOConfig)
+class TLGPIO(c: GPIOConfig)(implicit p: Parameters)
   extends TLRegisterRouter(c.address, interrupts = c.width, beatBytes = p(PeripheryBusConfig).beatBytes)(
-  new TLRegBundle(Tuple2(p, c), _)    with GPIOBundle)(
-  new TLRegModule(Tuple2(p, c), _, _) with GPIOModule)
+  new TLRegBundle(c, _)    with GPIOBundle)(
+  new TLRegModule(c, _, _) with GPIOModule)