X-Git-Url: https://git.libre-soc.org/?a=blobdiff_plain;ds=sidebyside;f=src%2Fmem%2Fcache%2Fprefetch%2FPrefetcher.py;h=c7ddcda1c2d1bcdcbe2c790d9ed0428da65d0aee;hb=7e19b26f503435f07dc4b5675061facc521b8c91;hp=3810b6afd3d6856fa42d6fa19e9ec9d397425ff7;hpb=b4c472945a6313e1ae1f4ba01477360c372dea6b;p=gem5.git diff --git a/src/mem/cache/prefetch/Prefetcher.py b/src/mem/cache/prefetch/Prefetcher.py index 3810b6afd..c7ddcda1c 100644 --- a/src/mem/cache/prefetch/Prefetcher.py +++ b/src/mem/cache/prefetch/Prefetcher.py @@ -65,6 +65,7 @@ class BasePrefetcher(ClockedObject): cxx_header = "mem/cache/prefetch/base.hh" cxx_exports = [ PyBindMethod("addEventProbe"), + PyBindMethod("addTLB"), ] sys = Param.System(Parent.any, "System this prefetcher belongs to") @@ -88,6 +89,8 @@ class BasePrefetcher(ClockedObject): # Override the normal SimObject::regProbeListeners method and # register deferred event handlers. def regProbeListeners(self): + for tlb in self._tlbs: + self.getCCObject().addTLB(tlb.getCCObject()) for event in self._events: event.register() self.getCCObject().regProbeListeners() @@ -98,6 +101,11 @@ class BasePrefetcher(ClockedObject): if len(probeNames) <= 0: raise TypeError("probeNames must have at least one element") self.addEvent(HWPProbeEvent(self, simObj, *probeNames)) + _tlbs = [] + def registerTLB(self, simObj): + if not isinstance(simObj, SimObject): + raise TypeError("argument must be a SimObject type") + self._tlbs.append(simObj) class MultiPrefetcher(BasePrefetcher): type = 'MultiPrefetcher' @@ -113,12 +121,26 @@ class QueuedPrefetcher(BasePrefetcher): cxx_header = "mem/cache/prefetch/queued.hh" latency = Param.Int(1, "Latency for generated prefetches") queue_size = Param.Int(32, "Maximum number of queued prefetches") + max_prefetch_requests_with_pending_translation = Param.Int(32, + "Maximum number of queued prefetches that have a missing translation") queue_squash = Param.Bool(True, "Squash queued prefetch on demand access") queue_filter = Param.Bool(True, "Don't queue redundant prefetches") cache_snoop = Param.Bool(False, "Snoop cache to eliminate redundant request") tag_prefetch = Param.Bool(True, "Tag prefetch with PC of generating access") + # The throttle_control_percentage controls how many of the candidate + # addresses generated by the prefetcher will be finally turned into + # prefetch requests + # - If set to 100, all candidates can be discarded (one request + # will always be allowed to be generated) + # - Setting it to 0 will disable the throttle control, so requests are + # created for all candidates + # - If set to 60, 40% of candidates will generate a request, and the + # remaining 60% will be generated depending on the current accuracy + throttle_control_percentage = Param.Percent(0, "Percentage of requests \ + that can be throttled depending on the accuracy of the prefetcher.") + class StridePrefetcher(QueuedPrefetcher): type = 'StridePrefetcher' cxx_class = 'StridePrefetcher'