X-Git-Url: https://git.libre-soc.org/?a=blobdiff_plain;ds=sidebyside;f=src%2Fmesa%2Fdrivers%2Fdri%2Fi965%2Fbrw_ir_vec4.h;h=81b6a139f4490950633d4627a4342a8e18ba3c8f;hb=c5f224145a41079ddcc77c0d7df8b4b75ed2d4fe;hp=955a62d5f9ef804f6220c6bd8d7dbc9af448c9a0;hpb=28e9601d0e681411b60a7de8be9f401b0df77d29;p=mesa.git diff --git a/src/mesa/drivers/dri/i965/brw_ir_vec4.h b/src/mesa/drivers/dri/i965/brw_ir_vec4.h index 955a62d5f9e..81b6a139f44 100644 --- a/src/mesa/drivers/dri/i965/brw_ir_vec4.h +++ b/src/mesa/drivers/dri/i965/brw_ir_vec4.h @@ -39,14 +39,9 @@ public: void init(); - src_reg(register_file file, int reg, const glsl_type *type); + src_reg(enum brw_reg_file file, int nr, const glsl_type *type); src_reg(); - src_reg(float f); - src_reg(uint32_t u); - src_reg(int32_t i); - src_reg(uint8_t vf[4]); - src_reg(uint8_t vf0, uint8_t vf1, uint8_t vf2, uint8_t vf3); - src_reg(struct brw_reg reg); + src_reg(struct ::brw_reg reg); bool equals(const src_reg &r) const; @@ -55,22 +50,21 @@ public: explicit src_reg(const dst_reg ®); - unsigned swizzle; /**< BRW_SWIZZLE_XYZW macros from brw_reg.h. */ - src_reg *reladdr; }; static inline src_reg retype(src_reg reg, enum brw_reg_type type) { - reg.fixed_hw_reg.type = reg.type = type; + reg.type = type; return reg; } static inline src_reg offset(src_reg reg, unsigned delta) { - assert(delta == 0 || (reg.file != HW_REG && reg.file != IMM)); + assert(delta == 0 || + (reg.file != ARF && reg.file != FIXED_GRF && reg.file != IMM)); reg.reg_offset += delta; return reg; } @@ -82,19 +76,29 @@ offset(src_reg reg, unsigned delta) static inline src_reg swizzle(src_reg reg, unsigned swizzle) { - assert(reg.file != HW_REG); - reg.swizzle = brw_compose_swizzle(swizzle, reg.swizzle); + if (reg.file == IMM) + reg.ud = brw_swizzle_immediate(reg.type, reg.ud, swizzle); + else + reg.swizzle = brw_compose_swizzle(swizzle, reg.swizzle); + return reg; } static inline src_reg negate(src_reg reg) { - assert(reg.file != HW_REG && reg.file != IMM); + assert(reg.file != IMM); reg.negate = !reg.negate; return reg; } +static inline bool +is_uniform(const src_reg ®) +{ + return (reg.file == IMM || reg.file == UNIFORM || reg.is_null()) && + (!reg.reladdr || is_uniform(*reg.reladdr)); +} + class dst_reg : public backend_reg { public: @@ -103,32 +107,33 @@ public: void init(); dst_reg(); - dst_reg(register_file file, int reg); - dst_reg(register_file file, int reg, const glsl_type *type, + dst_reg(enum brw_reg_file file, int nr); + dst_reg(enum brw_reg_file file, int nr, const glsl_type *type, + unsigned writemask); + dst_reg(enum brw_reg_file file, int nr, brw_reg_type type, unsigned writemask); - dst_reg(struct brw_reg reg); + dst_reg(struct ::brw_reg reg); dst_reg(class vec4_visitor *v, const struct glsl_type *type); explicit dst_reg(const src_reg ®); bool equals(const dst_reg &r) const; - unsigned writemask; /**< Bitfield of WRITEMASK_[XYZW] */ - src_reg *reladdr; }; static inline dst_reg retype(dst_reg reg, enum brw_reg_type type) { - reg.fixed_hw_reg.type = reg.type = type; + reg.type = type; return reg; } static inline dst_reg offset(dst_reg reg, unsigned delta) { - assert(delta == 0 || (reg.file != HW_REG && reg.file != IMM)); + assert(delta == 0 || + (reg.file != ARF && reg.file != FIXED_GRF && reg.file != IMM)); reg.reg_offset += delta; return reg; } @@ -136,7 +141,7 @@ offset(dst_reg reg, unsigned delta) static inline dst_reg writemask(dst_reg reg, unsigned mask) { - assert(reg.file != HW_REG && reg.file != IMM); + assert(reg.file != IMM); assert((reg.writemask & mask) != 0); reg.writemask &= mask; return reg; @@ -152,9 +157,6 @@ public: const src_reg &src1 = src_reg(), const src_reg &src2 = src_reg()); - struct brw_reg get_dst(void); - struct brw_reg get_src(const struct brw_vue_prog_data *prog_data, int i); - dst_reg dst; src_reg src[3]; @@ -166,15 +168,40 @@ public: bool is_send_from_grf(); unsigned regs_read(unsigned arg) const; - bool can_reswizzle(int dst_writemask, int swizzle, int swizzle_mask); + bool can_reswizzle(const struct brw_device_info *devinfo, int dst_writemask, + int swizzle, int swizzle_mask); void reswizzle(int dst_writemask, int swizzle); bool can_do_source_mods(const struct brw_device_info *devinfo); + bool can_do_writemask(const struct brw_device_info *devinfo); + bool can_change_types() const; + bool has_source_and_destination_hazard() const; bool reads_flag() { return predicate || opcode == VS_OPCODE_UNPACK_FLAGS_SIMD4X2; } + bool reads_flag(unsigned c) + { + if (opcode == VS_OPCODE_UNPACK_FLAGS_SIMD4X2) + return true; + + switch (predicate) { + case BRW_PREDICATE_NONE: + return false; + case BRW_PREDICATE_ALIGN16_REPLICATE_X: + return c == 0; + case BRW_PREDICATE_ALIGN16_REPLICATE_Y: + return c == 1; + case BRW_PREDICATE_ALIGN16_REPLICATE_Z: + return c == 2; + case BRW_PREDICATE_ALIGN16_REPLICATE_W: + return c == 3; + default: + return true; + } + } + bool writes_flag() { return (conditional_mod && (opcode != BRW_OPCODE_SEL && @@ -183,6 +210,50 @@ public: } }; +/** + * Make the execution of \p inst dependent on the evaluation of a possibly + * inverted predicate. + */ +inline vec4_instruction * +set_predicate_inv(enum brw_predicate pred, bool inverse, + vec4_instruction *inst) +{ + inst->predicate = pred; + inst->predicate_inverse = inverse; + return inst; +} + +/** + * Make the execution of \p inst dependent on the evaluation of a predicate. + */ +inline vec4_instruction * +set_predicate(enum brw_predicate pred, vec4_instruction *inst) +{ + return set_predicate_inv(pred, false, inst); +} + +/** + * Write the result of evaluating the condition given by \p mod to a flag + * register. + */ +inline vec4_instruction * +set_condmod(enum brw_conditional_mod mod, vec4_instruction *inst) +{ + inst->conditional_mod = mod; + return inst; +} + +/** + * Clamp the result of \p inst to the saturation range of its destination + * datatype. + */ +inline vec4_instruction * +set_saturate(bool saturate, vec4_instruction *inst) +{ + inst->saturate = saturate; + return inst; +} + } /* namespace brw */ #endif