X-Git-Url: https://git.libre-soc.org/?a=blobdiff_plain;ds=sidebyside;f=src%2Fmesa%2Fdrivers%2Fdri%2Fi965%2Fbrw_wm_surface_state.c;h=44c87df17d9ef2d2665a4262b41d1a1a17df0cc4;hb=27d0034938a8cee86a5a85cc22f610b1afdc9530;hp=a0ca6ddf9855d3e08beddc65eb24a36f1b291bf9;hpb=f6e674fa5164a957e93e8dc1334a48c9e7ee7df9;p=mesa.git diff --git a/src/mesa/drivers/dri/i965/brw_wm_surface_state.c b/src/mesa/drivers/dri/i965/brw_wm_surface_state.c index a0ca6ddf985..44c87df17d9 100644 --- a/src/mesa/drivers/dri/i965/brw_wm_surface_state.c +++ b/src/mesa/drivers/dri/i965/brw_wm_surface_state.c @@ -55,25 +55,28 @@ #include "brw_defines.h" #include "brw_wm.h" -enum { - INTEL_RENDERBUFFER_LAYERED = 1 << 0, - INTEL_AUX_BUFFER_DISABLED = 1 << 1, -}; - -uint32_t tex_mocs[] = { +uint32_t wb_mocs[] = { [7] = GEN7_MOCS_L3, [8] = BDW_MOCS_WB, [9] = SKL_MOCS_WB, [10] = CNL_MOCS_WB, + [11] = ICL_MOCS_WB, }; -uint32_t rb_mocs[] = { +uint32_t pte_mocs[] = { [7] = GEN7_MOCS_L3, [8] = BDW_MOCS_PTE, [9] = SKL_MOCS_PTE, [10] = CNL_MOCS_PTE, + [11] = ICL_MOCS_PTE, }; +uint32_t +brw_get_bo_mocs(const struct gen_device_info *devinfo, struct brw_bo *bo) +{ + return (bo && bo->external ? pte_mocs : wb_mocs)[devinfo->gen]; +} + static void get_isl_surf(struct brw_context *brw, struct intel_mipmap_tree *mt, GLenum target, struct isl_view *view, @@ -82,8 +85,9 @@ get_isl_surf(struct brw_context *brw, struct intel_mipmap_tree *mt, { *surf = mt->surf; + const struct gen_device_info *devinfo = &brw->screen->devinfo; const enum isl_dim_layout dim_layout = - get_isl_dim_layout(&brw->screen->devinfo, mt->surf.tiling, target); + get_isl_dim_layout(devinfo, mt->surf.tiling, target); if (surf->dim_layout == dim_layout) return; @@ -97,7 +101,7 @@ get_isl_surf(struct brw_context *brw, struct intel_mipmap_tree *mt, * texel of the level instead of relying on the usual base level/layer * controls. */ - assert(brw->has_surface_tile_offset); + assert(devinfo->has_surface_tile_offset); assert(view->levels == 1 && view->array_len == 1); assert(*tile_x == 0 && *tile_y == 0); @@ -132,9 +136,10 @@ brw_emit_surface_state(struct brw_context *brw, struct intel_mipmap_tree *mt, GLenum target, struct isl_view view, enum isl_aux_usage aux_usage, - uint32_t mocs, uint32_t *surf_offset, int surf_index, - unsigned read_domains, unsigned write_domains) + uint32_t *surf_offset, int surf_index, + unsigned reloc_flags) { + const struct gen_device_info *devinfo = &brw->screen->devinfo; uint32_t tile_x = mt->level[0].level_x; uint32_t tile_y = mt->level[0].level_y; uint32_t offset = mt->offset; @@ -154,13 +159,13 @@ brw_emit_surface_state(struct brw_context *brw, case ISL_AUX_USAGE_CCS_E: aux_surf = &mt->mcs_buf->surf; aux_bo = mt->mcs_buf->bo; - aux_offset = mt->mcs_buf->bo->offset64 + mt->mcs_buf->offset; + aux_offset = mt->mcs_buf->offset; break; case ISL_AUX_USAGE_HIZ: aux_surf = &mt->hiz_buf->surf; aux_bo = mt->hiz_buf->bo; - aux_offset = mt->hiz_buf->bo->offset64; + aux_offset = 0; break; case ISL_AUX_USAGE_NONE: @@ -180,50 +185,43 @@ brw_emit_surface_state(struct brw_context *brw, surf_offset); isl_surf_fill_state(&brw->isl_dev, state, .surf = &mt->surf, .view = &view, - .address = mt->bo->offset64 + offset, + .address = brw_state_reloc(&brw->batch, + *surf_offset + brw->isl_dev.ss.addr_offset, + mt->bo, offset, reloc_flags), .aux_surf = aux_surf, .aux_usage = aux_usage, .aux_address = aux_offset, - .mocs = mocs, .clear_color = clear_color, + .mocs = brw_get_bo_mocs(devinfo, mt->bo), + .clear_color = clear_color, .x_offset_sa = tile_x, .y_offset_sa = tile_y); - - brw_emit_reloc(&brw->batch, *surf_offset + brw->isl_dev.ss.addr_offset, - mt->bo, offset, read_domains, write_domains); - if (aux_surf) { /* On gen7 and prior, the upper 20 bits of surface state DWORD 6 are the * upper 20 bits of the GPU address of the MCS buffer; the lower 12 bits * contain other control information. Since buffer addresses are always * on 4k boundaries (and thus have their lower 12 bits zero), we can use * an ordinary reloc to do the necessary address translation. + * + * FIXME: move to the point of assignment. */ assert((aux_offset & 0xfff) == 0); uint32_t *aux_addr = state + brw->isl_dev.ss.aux_addr_offset; - brw_emit_reloc(&brw->batch, - *surf_offset + brw->isl_dev.ss.aux_addr_offset, - aux_bo, *aux_addr - aux_bo->offset64, - read_domains, write_domains); + *aux_addr = brw_state_reloc(&brw->batch, + *surf_offset + + brw->isl_dev.ss.aux_addr_offset, + aux_bo, *aux_addr, + reloc_flags); } } -uint32_t -brw_update_renderbuffer_surface(struct brw_context *brw, - struct gl_renderbuffer *rb, - uint32_t flags, unsigned unit, - uint32_t surf_index) +static uint32_t +gen6_update_renderbuffer_surface(struct brw_context *brw, + struct gl_renderbuffer *rb, + unsigned unit, + uint32_t surf_index) { struct gl_context *ctx = &brw->ctx; struct intel_renderbuffer *irb = intel_renderbuffer(rb); struct intel_mipmap_tree *mt = irb->mt; - enum isl_aux_usage aux_usage = - intel_miptree_render_aux_usage(brw, mt, ctx->Color.sRGBEnabled, - ctx->Color.BlendEnabled & (1 << unit)); - - if (flags & INTEL_AUX_BUFFER_DISABLED) { - assert(brw->gen >= 9); - aux_usage = ISL_AUX_USAGE_NONE; - } - assert(brw_render_target_supported(brw, rb)); mesa_format rb_format = _mesa_get_render_format(ctx, intel_rb_format(irb)); @@ -231,9 +229,10 @@ brw_update_renderbuffer_surface(struct brw_context *brw, _mesa_problem(ctx, "%s: renderbuffer format %s unsupported\n", __func__, _mesa_get_format_name(rb_format)); } + enum isl_format isl_format = brw->mesa_to_isl_render_format[rb_format]; struct isl_view view = { - .format = brw->mesa_to_isl_render_format[rb_format], + .format = isl_format, .base_level = irb->mt_level - irb->mt->first_level, .levels = 1, .base_array_layer = irb->mt_layer, @@ -243,11 +242,10 @@ brw_update_renderbuffer_surface(struct brw_context *brw, }; uint32_t offset; - brw_emit_surface_state(brw, mt, mt->target, view, aux_usage, - rb_mocs[brw->gen], + brw_emit_surface_state(brw, mt, mt->target, view, + brw->draw_aux_usage[unit], &offset, surf_index, - I915_GEM_DOMAIN_RENDER, - I915_GEM_DOMAIN_RENDER); + RELOC_WRITE); return offset; } @@ -441,31 +439,15 @@ swizzle_to_scs(GLenum swizzle, bool need_green_to_blue) return (need_green_to_blue && scs == HSW_SCS_GREEN) ? HSW_SCS_BLUE : scs; } -static bool -brw_aux_surface_disabled(const struct brw_context *brw, - const struct intel_mipmap_tree *mt) -{ - const struct gl_framebuffer *fb = brw->ctx.DrawBuffer; - - for (unsigned i = 0; i < fb->_NumColorDrawBuffers; i++) { - const struct intel_renderbuffer *irb = - intel_renderbuffer(fb->_ColorDrawBuffers[i]); - - if (irb && irb->mt == mt) - return brw->draw_aux_buffer_disabled[i]; - } - - return false; -} - -void -brw_update_texture_surface(struct gl_context *ctx, +static void brw_update_texture_surface(struct gl_context *ctx, unsigned unit, uint32_t *surf_offset, bool for_gather, + bool for_txf, uint32_t plane) { struct brw_context *brw = brw_context(ctx); + const struct gen_device_info *devinfo = &brw->screen->devinfo; struct gl_texture_object *obj = ctx->Texture.Unit[unit]._Current; if (obj->Target == GL_TEXTURE_BUFFER) { @@ -507,17 +489,18 @@ brw_update_texture_surface(struct gl_context *ctx, mesa_format mesa_fmt = plane == 0 ? intel_obj->_Format : mt->format; enum isl_format format = translate_tex_format(brw, mesa_fmt, + for_txf ? GL_DECODE_EXT : sampler->sRGBDecode); /* Implement gen6 and gen7 gather work-around */ bool need_green_to_blue = false; if (for_gather) { - if (brw->gen == 7 && (format == ISL_FORMAT_R32G32_FLOAT || - format == ISL_FORMAT_R32G32_SINT || - format == ISL_FORMAT_R32G32_UINT)) { + if (devinfo->gen == 7 && (format == ISL_FORMAT_R32G32_FLOAT || + format == ISL_FORMAT_R32G32_SINT || + format == ISL_FORMAT_R32G32_UINT)) { format = ISL_FORMAT_R32G32_FLOAT_LD; - need_green_to_blue = brw->is_haswell; - } else if (brw->gen == 6) { + need_green_to_blue = devinfo->is_haswell; + } else if (devinfo->gen == 6) { /* Sandybridge's gather4 message is broken for integer formats. * To work around this, we pretend the surface is UNORM for * 8 or 16-bit formats, and emit shader instructions to recover @@ -548,14 +531,14 @@ brw_update_texture_surface(struct gl_context *ctx, } if (obj->StencilSampling && firstImage->_BaseFormat == GL_DEPTH_STENCIL) { - if (brw->gen <= 7) { + if (devinfo->gen <= 7) { assert(mt->r8stencil_mt && !mt->stencil_mt->r8stencil_needs_update); mt = mt->r8stencil_mt; } else { mt = mt->stencil_mt; } format = ISL_FORMAT_R8_UINT; - } else if (brw->gen <= 7 && mt->format == MESA_FORMAT_S_UINT8) { + } else if (devinfo->gen <= 7 && mt->format == MESA_FORMAT_S_UINT8) { assert(mt->r8stencil_mt && !mt->r8stencil_needs_update); mt = mt->r8stencil_mt; format = ISL_FORMAT_R8_UINT; @@ -585,13 +568,9 @@ brw_update_texture_surface(struct gl_context *ctx, enum isl_aux_usage aux_usage = intel_miptree_texture_aux_usage(brw, mt, format); - if (brw_aux_surface_disabled(brw, mt)) - aux_usage = ISL_AUX_USAGE_NONE; - brw_emit_surface_state(brw, mt, mt->target, view, aux_usage, - tex_mocs[brw->gen], surf_offset, surf_index, - I915_GEM_DOMAIN_SAMPLER, 0); + 0); } } @@ -603,26 +582,24 @@ brw_emit_buffer_surface_state(struct brw_context *brw, unsigned surface_format, unsigned buffer_size, unsigned pitch, - bool rw) + unsigned reloc_flags) { + const struct gen_device_info *devinfo = &brw->screen->devinfo; uint32_t *dw = brw_state_batch(brw, brw->isl_dev.ss.size, brw->isl_dev.ss.align, out_offset); isl_buffer_fill_state(&brw->isl_dev, dw, - .address = (bo ? bo->offset64 : 0) + buffer_offset, + .address = !bo ? buffer_offset : + brw_state_reloc(&brw->batch, + *out_offset + brw->isl_dev.ss.addr_offset, + bo, buffer_offset, + reloc_flags), .size = buffer_size, .format = surface_format, .stride = pitch, - .mocs = tex_mocs[brw->gen]); - - if (bo) { - brw_emit_reloc(&brw->batch, *out_offset + brw->isl_dev.ss.addr_offset, - bo, buffer_offset, - I915_GEM_DOMAIN_SAMPLER, - (rw ? I915_GEM_DOMAIN_SAMPLER : 0)); - } + .mocs = brw_get_bo_mocs(devinfo, bo)); } void @@ -674,45 +651,7 @@ brw_update_buffer_texture_surface(struct gl_context *ctx, isl_format, size, texel_size, - false /* rw */); -} - -/** - * Create the constant buffer surface. Vertex/fragment shader constants will be - * read from this buffer with Data Port Read instructions/messages. - */ -void -brw_create_constant_surface(struct brw_context *brw, - struct brw_bo *bo, - uint32_t offset, - uint32_t size, - uint32_t *out_offset) -{ - brw_emit_buffer_surface_state(brw, out_offset, bo, offset, - ISL_FORMAT_R32G32B32A32_FLOAT, - size, 1, false); -} - -/** - * Create the buffer surface. Shader buffer variables will be - * read from / write to this buffer with Data Port Read/Write - * instructions/messages. - */ -void -brw_create_buffer_surface(struct brw_context *brw, - struct brw_bo *bo, - uint32_t offset, - uint32_t size, - uint32_t *out_offset) -{ - /* Use a raw surface so we can reuse existing untyped read/write/atomic - * messages. We need these specifically for the fragment shader since they - * include a pixel mask header that we need to ensure correct behavior - * with helper invocations, which cannot write to the buffer. - */ - brw_emit_buffer_surface_state(brw, out_offset, bo, offset, - ISL_FORMAT_RAW, - size, 1, true); + 0); } /** @@ -785,17 +724,14 @@ brw_update_sol_surface(struct brw_context *brw, BRW_SURFACE_MIPMAPLAYOUT_BELOW << BRW_SURFACE_MIPLAYOUT_SHIFT | surface_format << BRW_SURFACE_FORMAT_SHIFT | BRW_SURFACE_RC_READ_WRITE; - surf[1] = bo->offset64 + offset_bytes; /* reloc */ + surf[1] = brw_state_reloc(&brw->batch, + *out_offset + 4, bo, offset_bytes, RELOC_WRITE); surf[2] = (width << BRW_SURFACE_WIDTH_SHIFT | height << BRW_SURFACE_HEIGHT_SHIFT); surf[3] = (depth << BRW_SURFACE_DEPTH_SHIFT | pitch_minus_1 << BRW_SURFACE_PITCH_SHIFT); surf[4] = 0; surf[5] = 0; - - /* Emit relocation to surface contents. */ - brw_emit_reloc(&brw->batch, *out_offset + 4, bo, offset_bytes, - I915_GEM_DOMAIN_RENDER, I915_GEM_DOMAIN_RENDER); } /* Creates a new WM constant buffer reflecting the current fragment program's @@ -809,7 +745,9 @@ brw_upload_wm_pull_constants(struct brw_context *brw) { struct brw_stage_state *stage_state = &brw->wm.base; /* BRW_NEW_FRAGMENT_PROGRAM */ - struct brw_program *fp = (struct brw_program *) brw->fragment_program; + struct brw_program *fp = + (struct brw_program *) brw->programs[MESA_SHADER_FRAGMENT]; + /* BRW_NEW_FS_PROG_DATA */ struct brw_stage_prog_data *prog_data = brw->wm.base.prog_data; @@ -823,7 +761,6 @@ const struct brw_tracked_state brw_wm_pull_constants = { .dirty = { .mesa = _NEW_PROGRAM_CONSTANTS, .brw = BRW_NEW_BATCH | - BRW_NEW_BLORP | BRW_NEW_FRAGMENT_PROGRAM | BRW_NEW_FS_PROG_DATA, }, @@ -839,71 +776,53 @@ const struct brw_tracked_state brw_wm_pull_constants = { * hardware discard the target 0 color output.. */ static void -brw_emit_null_surface_state(struct brw_context *brw, - unsigned width, - unsigned height, - unsigned samples, - uint32_t *out_offset) +emit_null_surface_state(struct brw_context *brw, + const struct gl_framebuffer *fb, + uint32_t *out_offset) { - /* From the Sandy bridge PRM, Vol4 Part1 p71 (Surface Type: Programming - * Notes): - * - * A null surface will be used in instances where an actual surface is - * not bound. When a write message is generated to a null surface, no - * actual surface is written to. When a read message (including any - * sampling engine message) is generated to a null surface, the result - * is all zeros. Note that a null surface type is allowed to be used - * with all messages, even if it is not specificially indicated as - * supported. All of the remaining fields in surface state are ignored - * for null surfaces, with the following exceptions: + const struct gen_device_info *devinfo = &brw->screen->devinfo; + uint32_t *surf = brw_state_batch(brw, + brw->isl_dev.ss.size, + brw->isl_dev.ss.align, + out_offset); + + /* Use the fb dimensions or 1x1x1 */ + const unsigned width = fb ? _mesa_geometric_width(fb) : 1; + const unsigned height = fb ? _mesa_geometric_height(fb) : 1; + const unsigned samples = fb ? _mesa_geometric_samples(fb) : 1; + + if (devinfo->gen != 6 || samples <= 1) { + isl_null_fill_state(&brw->isl_dev, surf, + isl_extent3d(width, height, 1)); + return; + } + + /* On Gen6, null render targets seem to cause GPU hangs when multisampling. + * So work around this problem by rendering into dummy color buffer. * - * - [DevSNB+]: Width, Height, Depth, and LOD fields must match the - * depth buffer’s corresponding state for all render target surfaces, - * including null. + * To decrease the amount of memory needed by the workaround buffer, we + * set its pitch to 128 bytes (the width of a Y tile). This means that + * the amount of memory needed for the workaround buffer is + * (width_in_tiles + height_in_tiles - 1) tiles. * - * - Surface Format must be R8G8B8A8_UNORM. + * Note that since the workaround buffer will be interpreted by the + * hardware as an interleaved multisampled buffer, we need to compute + * width_in_tiles and height_in_tiles by dividing the width and height + * by 16 rather than the normal Y-tile size of 32. */ - unsigned surface_type = BRW_SURFACE_NULL; - struct brw_bo *bo = NULL; - unsigned pitch_minus_1 = 0; - uint32_t multisampling_state = 0; - uint32_t *surf = brw_state_batch(brw, 6 * 4, 32, out_offset); + unsigned width_in_tiles = ALIGN(width, 16) / 16; + unsigned height_in_tiles = ALIGN(height, 16) / 16; + unsigned pitch_minus_1 = 127; + unsigned size_needed = (width_in_tiles + height_in_tiles - 1) * 4096; + brw_get_scratch_bo(brw, &brw->wm.multisampled_null_render_target_bo, + size_needed); - if (samples > 1) { - /* On Gen6, null render targets seem to cause GPU hangs when - * multisampling. So work around this problem by rendering into dummy - * color buffer. - * - * To decrease the amount of memory needed by the workaround buffer, we - * set its pitch to 128 bytes (the width of a Y tile). This means that - * the amount of memory needed for the workaround buffer is - * (width_in_tiles + height_in_tiles - 1) tiles. - * - * Note that since the workaround buffer will be interpreted by the - * hardware as an interleaved multisampled buffer, we need to compute - * width_in_tiles and height_in_tiles by dividing the width and height - * by 16 rather than the normal Y-tile size of 32. - */ - unsigned width_in_tiles = ALIGN(width, 16) / 16; - unsigned height_in_tiles = ALIGN(height, 16) / 16; - unsigned size_needed = (width_in_tiles + height_in_tiles - 1) * 4096; - brw_get_scratch_bo(brw, &brw->wm.multisampled_null_render_target_bo, - size_needed); - bo = brw->wm.multisampled_null_render_target_bo; - surface_type = BRW_SURFACE_2D; - pitch_minus_1 = 127; - multisampling_state = brw_get_surface_num_multisamples(samples); - } - - surf[0] = (surface_type << BRW_SURFACE_TYPE_SHIFT | + surf[0] = (BRW_SURFACE_2D << BRW_SURFACE_TYPE_SHIFT | ISL_FORMAT_B8G8R8A8_UNORM << BRW_SURFACE_FORMAT_SHIFT); - if (brw->gen < 6) { - surf[0] |= (1 << BRW_SURFACE_WRITEDISABLE_R_SHIFT | - 1 << BRW_SURFACE_WRITEDISABLE_G_SHIFT | - 1 << BRW_SURFACE_WRITEDISABLE_B_SHIFT | - 1 << BRW_SURFACE_WRITEDISABLE_A_SHIFT); - } - surf[1] = bo ? bo->offset64 : 0; + surf[1] = brw_state_reloc(&brw->batch, *out_offset + 4, + brw->wm.multisampled_null_render_target_bo, + 0, RELOC_WRITE); + surf[2] = ((width - 1) << BRW_SURFACE_WIDTH_SHIFT | (height - 1) << BRW_SURFACE_HEIGHT_SHIFT); @@ -914,13 +833,8 @@ brw_emit_null_surface_state(struct brw_context *brw, */ surf[3] = (BRW_SURFACE_TILED | BRW_SURFACE_TILED_Y | pitch_minus_1 << BRW_SURFACE_PITCH_SHIFT); - surf[4] = multisampling_state; + surf[4] = BRW_SURFACE_MULTISAMPLECOUNT_4; surf[5] = 0; - - if (bo) { - brw_emit_reloc(&brw->batch, *out_offset + 4, bo, 0, - I915_GEM_DOMAIN_RENDER, I915_GEM_DOMAIN_RENDER); - } } /** @@ -931,9 +845,10 @@ brw_emit_null_surface_state(struct brw_context *brw, static uint32_t gen4_update_renderbuffer_surface(struct brw_context *brw, struct gl_renderbuffer *rb, - uint32_t flags, unsigned unit, + unsigned unit, uint32_t surf_index) { + const struct gen_device_info *devinfo = &brw->screen->devinfo; struct gl_context *ctx = &brw->ctx; struct intel_renderbuffer *irb = intel_renderbuffer(rb); struct intel_mipmap_tree *mt = irb->mt; @@ -945,10 +860,7 @@ gen4_update_renderbuffer_surface(struct brw_context *brw, mesa_format rb_format = _mesa_get_render_format(ctx, intel_rb_format(irb)); /* BRW_NEW_FS_PROG_DATA */ - assert(!(flags & INTEL_RENDERBUFFER_LAYERED)); - assert(!(flags & INTEL_AUX_BUFFER_DISABLED)); - - if (rb->TexImage && !brw->has_surface_tile_offset) { + if (rb->TexImage && !devinfo->has_surface_tile_offset) { intel_renderbuffer_get_tile_offsets(irb, &tile_x, &tile_y); if (tile_x != 0 || tile_y != 0) { @@ -977,8 +889,12 @@ gen4_update_renderbuffer_surface(struct brw_context *brw, /* reloc */ assert(mt->offset % mt->cpp == 0); - surf[1] = (intel_renderbuffer_get_tile_offsets(irb, &tile_x, &tile_y) + - mt->bo->offset64 + mt->offset); + surf[1] = brw_state_reloc(&brw->batch, offset + 4, mt->bo, + mt->offset + + intel_renderbuffer_get_tile_offsets(irb, + &tile_x, + &tile_y), + RELOC_WRITE); surf[2] = ((rb->Width - 1) << BRW_SURFACE_WIDTH_SHIFT | (rb->Height - 1) << BRW_SURFACE_HEIGHT_SHIFT); @@ -988,7 +904,7 @@ gen4_update_renderbuffer_surface(struct brw_context *brw, surf[4] = brw_get_surface_num_multisamples(mt->surf.samples); - assert(brw->has_surface_tile_offset || (tile_x == 0 && tile_y == 0)); + assert(devinfo->has_surface_tile_offset || (tile_x == 0 && tile_y == 0)); /* Note that the low bits of these fields are missing, so * there's the possibility of getting in trouble. */ @@ -999,88 +915,62 @@ gen4_update_renderbuffer_surface(struct brw_context *brw, (mt->surf.image_alignment_el.height == 4 ? BRW_SURFACE_VERTICAL_ALIGN_ENABLE : 0)); - if (brw->gen < 6) { + if (devinfo->gen < 6) { /* _NEW_COLOR */ if (!ctx->Color.ColorLogicOpEnabled && !ctx->Color._AdvancedBlendMode && (ctx->Color.BlendEnabled & (1 << unit))) surf[0] |= BRW_SURFACE_BLEND_ENABLED; - if (!ctx->Color.ColorMask[unit][0]) + if (!GET_COLORMASK_BIT(ctx->Color.ColorMask, unit, 0)) surf[0] |= 1 << BRW_SURFACE_WRITEDISABLE_R_SHIFT; - if (!ctx->Color.ColorMask[unit][1]) + if (!GET_COLORMASK_BIT(ctx->Color.ColorMask, unit, 1)) surf[0] |= 1 << BRW_SURFACE_WRITEDISABLE_G_SHIFT; - if (!ctx->Color.ColorMask[unit][2]) + if (!GET_COLORMASK_BIT(ctx->Color.ColorMask, unit, 2)) surf[0] |= 1 << BRW_SURFACE_WRITEDISABLE_B_SHIFT; /* As mentioned above, disable writes to the alpha component when the * renderbuffer is XRGB. */ if (ctx->DrawBuffer->Visual.alphaBits == 0 || - !ctx->Color.ColorMask[unit][3]) { + !GET_COLORMASK_BIT(ctx->Color.ColorMask, unit, 3)) { surf[0] |= 1 << BRW_SURFACE_WRITEDISABLE_A_SHIFT; } } - brw_emit_reloc(&brw->batch, offset + 4, mt->bo, surf[1] - mt->bo->offset64, - I915_GEM_DOMAIN_RENDER, I915_GEM_DOMAIN_RENDER); - return offset; } -/** - * Construct SURFACE_STATE objects for renderbuffers/draw buffers. - */ -void -brw_update_renderbuffer_surfaces(struct brw_context *brw, - const struct gl_framebuffer *fb, - uint32_t render_target_start, - uint32_t *surf_offset) +static void +update_renderbuffer_surfaces(struct brw_context *brw) { - GLuint i; - const unsigned int w = _mesa_geometric_width(fb); - const unsigned int h = _mesa_geometric_height(fb); - const unsigned int s = _mesa_geometric_samples(fb); + const struct gen_device_info *devinfo = &brw->screen->devinfo; + const struct gl_context *ctx = &brw->ctx; + + /* _NEW_BUFFERS | _NEW_COLOR */ + const struct gl_framebuffer *fb = ctx->DrawBuffer; + + /* Render targets always start at binding table index 0. */ + const unsigned rt_start = 0; + + uint32_t *surf_offsets = brw->wm.base.surf_offset; /* Update surfaces for drawing buffers */ if (fb->_NumColorDrawBuffers >= 1) { - for (i = 0; i < fb->_NumColorDrawBuffers; i++) { - const uint32_t surf_index = render_target_start + i; - const int flags = (_mesa_geometric_layers(fb) > 0 ? - INTEL_RENDERBUFFER_LAYERED : 0) | - (brw->draw_aux_buffer_disabled[i] ? - INTEL_AUX_BUFFER_DISABLED : 0); - - if (intel_renderbuffer(fb->_ColorDrawBuffers[i])) { - surf_offset[surf_index] = - brw->vtbl.update_renderbuffer_surface( - brw, fb->_ColorDrawBuffers[i], flags, i, surf_index); + for (unsigned i = 0; i < fb->_NumColorDrawBuffers; i++) { + struct gl_renderbuffer *rb = fb->_ColorDrawBuffers[i]; + + if (intel_renderbuffer(rb)) { + surf_offsets[rt_start + i] = devinfo->gen >= 6 ? + gen6_update_renderbuffer_surface(brw, rb, i, rt_start + i) : + gen4_update_renderbuffer_surface(brw, rb, i, rt_start + i); } else { - brw->vtbl.emit_null_surface_state(brw, w, h, s, - &surf_offset[surf_index]); + emit_null_surface_state(brw, fb, &surf_offsets[rt_start + i]); } } } else { - const uint32_t surf_index = render_target_start; - brw->vtbl.emit_null_surface_state(brw, w, h, s, - &surf_offset[surf_index]); + emit_null_surface_state(brw, fb, &surf_offsets[rt_start]); } -} - -static void -update_renderbuffer_surfaces(struct brw_context *brw) -{ - const struct gl_context *ctx = &brw->ctx; - - /* BRW_NEW_FS_PROG_DATA */ - const struct brw_wm_prog_data *wm_prog_data = - brw_wm_prog_data(brw->wm.base.prog_data); - /* _NEW_BUFFERS | _NEW_COLOR */ - const struct gl_framebuffer *fb = ctx->DrawBuffer; - brw_update_renderbuffer_surfaces( - brw, fb, - wm_prog_data->binding_table.render_target_start, - brw->wm.base.surf_offset); brw->ctx.NewDriverState |= BRW_NEW_SURFACES; } @@ -1088,9 +978,7 @@ const struct brw_tracked_state brw_renderbuffer_surfaces = { .dirty = { .mesa = _NEW_BUFFERS | _NEW_COLOR, - .brw = BRW_NEW_BATCH | - BRW_NEW_BLORP | - BRW_NEW_FS_PROG_DATA, + .brw = BRW_NEW_BATCH, }, .emit = update_renderbuffer_surfaces, }; @@ -1099,7 +987,7 @@ const struct brw_tracked_state gen6_renderbuffer_surfaces = { .dirty = { .mesa = _NEW_BUFFERS, .brw = BRW_NEW_BATCH | - BRW_NEW_BLORP, + BRW_NEW_AUX_STATE, }, .emit = update_renderbuffer_surfaces, }; @@ -1113,9 +1001,8 @@ update_renderbuffer_read_surfaces(struct brw_context *brw) const struct brw_wm_prog_data *wm_prog_data = brw_wm_prog_data(brw->wm.base.prog_data); - /* BRW_NEW_FRAGMENT_PROGRAM */ - if (!ctx->Extensions.MESA_shader_framebuffer_fetch && - brw->fragment_program && brw->fragment_program->info.outputs_read) { + if (wm_prog_data->has_render_target_reads && + !ctx->Extensions.MESA_shader_framebuffer_fetch) { /* _NEW_BUFFERS */ const struct gl_framebuffer *fb = ctx->DrawBuffer; @@ -1159,18 +1046,15 @@ update_renderbuffer_read_surfaces(struct brw_context *brw) enum isl_aux_usage aux_usage = intel_miptree_texture_aux_usage(brw, irb->mt, format); - if (brw->draw_aux_buffer_disabled[i]) + if (brw->draw_aux_usage[i] == ISL_AUX_USAGE_NONE) aux_usage = ISL_AUX_USAGE_NONE; brw_emit_surface_state(brw, irb->mt, target, view, aux_usage, - tex_mocs[brw->gen], surf_offset, surf_index, - I915_GEM_DOMAIN_SAMPLER, 0); + 0); } else { - brw->vtbl.emit_null_surface_state( - brw, _mesa_geometric_width(fb), _mesa_geometric_height(fb), - _mesa_geometric_samples(fb), surf_offset); + emit_null_surface_state(brw, fb, surf_offset); } } @@ -1182,12 +1066,20 @@ const struct brw_tracked_state brw_renderbuffer_read_surfaces = { .dirty = { .mesa = _NEW_BUFFERS, .brw = BRW_NEW_BATCH | - BRW_NEW_FRAGMENT_PROGRAM | + BRW_NEW_AUX_STATE | BRW_NEW_FS_PROG_DATA, }, .emit = update_renderbuffer_read_surfaces, }; +static bool +is_depth_texture(struct intel_texture_object *iobj) +{ + GLenum base_format = _mesa_get_format_base_format(iobj->_Format); + return base_format == GL_DEPTH_COMPONENT || + (base_format == GL_DEPTH_STENCIL && !iobj->base.StencilSampling); +} + static void update_stage_texture_surfaces(struct brw_context *brw, const struct gl_program *prog, @@ -1213,10 +1105,35 @@ update_stage_texture_surfaces(struct brw_context *brw, if (prog->SamplersUsed & (1 << s)) { const unsigned unit = prog->SamplerUnits[s]; + const bool used_by_txf = prog->info.textures_used_by_txf & (1 << s); + struct gl_texture_object *obj = ctx->Texture.Unit[unit]._Current; + struct intel_texture_object *iobj = intel_texture_object(obj); /* _NEW_TEXTURE */ - if (ctx->Texture.Unit[unit]._Current) { - brw_update_texture_surface(ctx, unit, surf_offset + s, for_gather, plane); + if (!obj) + continue; + + if ((prog->ShadowSamplers & (1 << s)) && !is_depth_texture(iobj)) { + /* A programming note for the sample_c message says: + * + * "The Surface Format of the associated surface must be + * indicated as supporting shadow mapping as indicated in the + * surface format table." + * + * Accessing non-depth textures via a sampler*Shadow type is + * undefined. GLSL 4.50 page 162 says: + * + * "If a shadow texture call is made to a sampler that does not + * represent a depth texture, then results are undefined." + * + * We give them a null surface (zeros) for undefined. We've seen + * GPU hangs with color buffers and sample_c, so we try and avoid + * those with this hack. + */ + emit_null_surface_state(brw, NULL, surf_offset + s); + } else { + brw_update_texture_surface(ctx, unit, surf_offset + s, for_gather, + used_by_txf, plane); } } } @@ -1229,18 +1146,20 @@ update_stage_texture_surfaces(struct brw_context *brw, static void brw_update_texture_surfaces(struct brw_context *brw) { + const struct gen_device_info *devinfo = &brw->screen->devinfo; + /* BRW_NEW_VERTEX_PROGRAM */ - struct gl_program *vs = (struct gl_program *) brw->vertex_program; + struct gl_program *vs = brw->programs[MESA_SHADER_VERTEX]; /* BRW_NEW_TESS_PROGRAMS */ - struct gl_program *tcs = (struct gl_program *) brw->tess_ctrl_program; - struct gl_program *tes = (struct gl_program *) brw->tess_eval_program; + struct gl_program *tcs = brw->programs[MESA_SHADER_TESS_CTRL]; + struct gl_program *tes = brw->programs[MESA_SHADER_TESS_EVAL]; /* BRW_NEW_GEOMETRY_PROGRAM */ - struct gl_program *gs = (struct gl_program *) brw->geometry_program; + struct gl_program *gs = brw->programs[MESA_SHADER_GEOMETRY]; /* BRW_NEW_FRAGMENT_PROGRAM */ - struct gl_program *fs = (struct gl_program *) brw->fragment_program; + struct gl_program *fs = brw->programs[MESA_SHADER_FRAGMENT]; /* _NEW_TEXTURE */ update_stage_texture_surfaces(brw, vs, &brw->vs.base, false, 0); @@ -1252,16 +1171,16 @@ brw_update_texture_surfaces(struct brw_context *brw) /* emit alternate set of surface state for gather. this * allows the surface format to be overriden for only the * gather4 messages. */ - if (brw->gen < 8) { - if (vs && vs->nir->info.uses_texture_gather) + if (devinfo->gen < 8) { + if (vs && vs->info.uses_texture_gather) update_stage_texture_surfaces(brw, vs, &brw->vs.base, true, 0); - if (tcs && tcs->nir->info.uses_texture_gather) + if (tcs && tcs->info.uses_texture_gather) update_stage_texture_surfaces(brw, tcs, &brw->tcs.base, true, 0); - if (tes && tes->nir->info.uses_texture_gather) + if (tes && tes->info.uses_texture_gather) update_stage_texture_surfaces(brw, tes, &brw->tes.base, true, 0); - if (gs && gs->nir->info.uses_texture_gather) + if (gs && gs->info.uses_texture_gather) update_stage_texture_surfaces(brw, gs, &brw->gs.base, true, 0); - if (fs && fs->nir->info.uses_texture_gather) + if (fs && fs->info.uses_texture_gather) update_stage_texture_surfaces(brw, fs, &brw->wm.base, true, 0); } @@ -1277,7 +1196,7 @@ const struct brw_tracked_state brw_texture_surfaces = { .dirty = { .mesa = _NEW_TEXTURE, .brw = BRW_NEW_BATCH | - BRW_NEW_BLORP | + BRW_NEW_AUX_STATE | BRW_NEW_FRAGMENT_PROGRAM | BRW_NEW_FS_PROG_DATA | BRW_NEW_GEOMETRY_PROGRAM | @@ -1295,8 +1214,10 @@ const struct brw_tracked_state brw_texture_surfaces = { static void brw_update_cs_texture_surfaces(struct brw_context *brw) { + const struct gen_device_info *devinfo = &brw->screen->devinfo; + /* BRW_NEW_COMPUTE_PROGRAM */ - struct gl_program *cs = (struct gl_program *) brw->compute_program; + struct gl_program *cs = brw->programs[MESA_SHADER_COMPUTE]; /* _NEW_TEXTURE */ update_stage_texture_surfaces(brw, cs, &brw->cs.base, false, 0); @@ -1305,8 +1226,8 @@ brw_update_cs_texture_surfaces(struct brw_context *brw) * allows the surface format to be overriden for only the * gather4 messages. */ - if (brw->gen < 8) { - if (cs && cs->nir->info.uses_texture_gather) + if (devinfo->gen < 8) { + if (cs && cs->info.uses_texture_gather) update_stage_texture_surfaces(brw, cs, &brw->cs.base, true, 0); } @@ -1317,12 +1238,38 @@ const struct brw_tracked_state brw_cs_texture_surfaces = { .dirty = { .mesa = _NEW_TEXTURE, .brw = BRW_NEW_BATCH | - BRW_NEW_BLORP | - BRW_NEW_COMPUTE_PROGRAM, + BRW_NEW_COMPUTE_PROGRAM | + BRW_NEW_AUX_STATE, }, .emit = brw_update_cs_texture_surfaces, }; +static void +upload_buffer_surface(struct brw_context *brw, + struct gl_buffer_binding *binding, + uint32_t *out_offset, + enum isl_format format, + unsigned reloc_flags) +{ + struct gl_context *ctx = &brw->ctx; + + if (binding->BufferObject == ctx->Shared->NullBufferObj) { + emit_null_surface_state(brw, NULL, out_offset); + } else { + ptrdiff_t size = binding->BufferObject->Size - binding->Offset; + if (!binding->AutomaticSize) + size = MIN2(size, binding->Size); + + struct intel_buffer_object *iobj = + intel_buffer_object(binding->BufferObject); + struct brw_bo *bo = + intel_bufferobj_buffer(brw, iobj, binding->Offset, size, + (reloc_flags & RELOC_WRITE) != 0); + + brw_emit_buffer_surface_state(brw, out_offset, bo, binding->Offset, + format, size, 1, reloc_flags); + } +} void brw_upload_ubo_surfaces(struct brw_context *brw, struct gl_program *prog, @@ -1331,63 +1278,42 @@ brw_upload_ubo_surfaces(struct brw_context *brw, struct gl_program *prog, { struct gl_context *ctx = &brw->ctx; - if (!prog) + if (!prog || (prog->info.num_ubos == 0 && + prog->info.num_ssbos == 0 && + prog->info.num_abos == 0)) return; uint32_t *ubo_surf_offsets = &stage_state->surf_offset[prog_data->binding_table.ubo_start]; for (int i = 0; i < prog->info.num_ubos; i++) { - struct gl_uniform_buffer_binding *binding = + struct gl_buffer_binding *binding = &ctx->UniformBufferBindings[prog->sh.UniformBlocks[i]->Binding]; - - if (binding->BufferObject == ctx->Shared->NullBufferObj) { - brw->vtbl.emit_null_surface_state(brw, 1, 1, 1, &ubo_surf_offsets[i]); - } else { - struct intel_buffer_object *intel_bo = - intel_buffer_object(binding->BufferObject); - GLsizeiptr size = binding->BufferObject->Size - binding->Offset; - if (!binding->AutomaticSize) - size = MIN2(size, binding->Size); - struct brw_bo *bo = - intel_bufferobj_buffer(brw, intel_bo, - binding->Offset, - size, false); - brw_create_constant_surface(brw, bo, binding->Offset, - size, - &ubo_surf_offsets[i]); - } + upload_buffer_surface(brw, binding, &ubo_surf_offsets[i], + ISL_FORMAT_R32G32B32A32_FLOAT, 0); } - uint32_t *ssbo_surf_offsets = + uint32_t *abo_surf_offsets = &stage_state->surf_offset[prog_data->binding_table.ssbo_start]; + uint32_t *ssbo_surf_offsets = abo_surf_offsets + prog->info.num_abos; + + for (int i = 0; i < prog->info.num_abos; i++) { + struct gl_buffer_binding *binding = + &ctx->AtomicBufferBindings[prog->sh.AtomicBuffers[i]->Binding]; + upload_buffer_surface(brw, binding, &abo_surf_offsets[i], + ISL_FORMAT_RAW, RELOC_WRITE); + } for (int i = 0; i < prog->info.num_ssbos; i++) { - struct gl_shader_storage_buffer_binding *binding = + struct gl_buffer_binding *binding = &ctx->ShaderStorageBufferBindings[prog->sh.ShaderStorageBlocks[i]->Binding]; - if (binding->BufferObject == ctx->Shared->NullBufferObj) { - brw->vtbl.emit_null_surface_state(brw, 1, 1, 1, &ssbo_surf_offsets[i]); - } else { - struct intel_buffer_object *intel_bo = - intel_buffer_object(binding->BufferObject); - GLsizeiptr size = binding->BufferObject->Size - binding->Offset; - if (!binding->AutomaticSize) - size = MIN2(size, binding->Size); - struct brw_bo *bo = - intel_bufferobj_buffer(brw, intel_bo, - binding->Offset, - size, true); - brw_create_buffer_surface(brw, bo, binding->Offset, - size, - &ssbo_surf_offsets[i]); - } + upload_buffer_surface(brw, binding, &ssbo_surf_offsets[i], + ISL_FORMAT_RAW, RELOC_WRITE); } stage_state->push_constants_dirty = true; - - if (prog->info.num_ubos || prog->info.num_ssbos) - brw->ctx.NewDriverState |= BRW_NEW_SURFACES; + brw->ctx.NewDriverState |= BRW_NEW_SURFACES; } static void @@ -1405,7 +1331,6 @@ const struct brw_tracked_state brw_wm_ubo_surfaces = { .dirty = { .mesa = _NEW_PROGRAM, .brw = BRW_NEW_BATCH | - BRW_NEW_BLORP | BRW_NEW_FS_PROG_DATA | BRW_NEW_UNIFORM_BUFFER, }, @@ -1428,94 +1353,17 @@ const struct brw_tracked_state brw_cs_ubo_surfaces = { .dirty = { .mesa = _NEW_PROGRAM, .brw = BRW_NEW_BATCH | - BRW_NEW_BLORP | BRW_NEW_CS_PROG_DATA | BRW_NEW_UNIFORM_BUFFER, }, .emit = brw_upload_cs_ubo_surfaces, }; -void -brw_upload_abo_surfaces(struct brw_context *brw, - const struct gl_program *prog, - struct brw_stage_state *stage_state, - struct brw_stage_prog_data *prog_data) -{ - struct gl_context *ctx = &brw->ctx; - uint32_t *surf_offsets = - &stage_state->surf_offset[prog_data->binding_table.abo_start]; - - if (prog->info.num_abos) { - for (unsigned i = 0; i < prog->info.num_abos; i++) { - struct gl_atomic_buffer_binding *binding = - &ctx->AtomicBufferBindings[prog->sh.AtomicBuffers[i]->Binding]; - struct intel_buffer_object *intel_bo = - intel_buffer_object(binding->BufferObject); - struct brw_bo *bo = - intel_bufferobj_buffer(brw, intel_bo, binding->Offset, - intel_bo->Base.Size - binding->Offset, - true); - - brw_emit_buffer_surface_state(brw, &surf_offsets[i], bo, - binding->Offset, ISL_FORMAT_RAW, - bo->size - binding->Offset, 1, true); - } - - brw->ctx.NewDriverState |= BRW_NEW_SURFACES; - } -} - -static void -brw_upload_wm_abo_surfaces(struct brw_context *brw) -{ - /* _NEW_PROGRAM */ - const struct gl_program *wm = brw->fragment_program; - - if (wm) { - /* BRW_NEW_FS_PROG_DATA */ - brw_upload_abo_surfaces(brw, wm, &brw->wm.base, brw->wm.base.prog_data); - } -} - -const struct brw_tracked_state brw_wm_abo_surfaces = { - .dirty = { - .mesa = _NEW_PROGRAM, - .brw = BRW_NEW_ATOMIC_BUFFER | - BRW_NEW_BLORP | - BRW_NEW_BATCH | - BRW_NEW_FS_PROG_DATA, - }, - .emit = brw_upload_wm_abo_surfaces, -}; - -static void -brw_upload_cs_abo_surfaces(struct brw_context *brw) -{ - /* _NEW_PROGRAM */ - const struct gl_program *cp = brw->compute_program; - - if (cp) { - /* BRW_NEW_CS_PROG_DATA */ - brw_upload_abo_surfaces(brw, cp, &brw->cs.base, brw->cs.base.prog_data); - } -} - -const struct brw_tracked_state brw_cs_abo_surfaces = { - .dirty = { - .mesa = _NEW_PROGRAM, - .brw = BRW_NEW_ATOMIC_BUFFER | - BRW_NEW_BLORP | - BRW_NEW_BATCH | - BRW_NEW_CS_PROG_DATA, - }, - .emit = brw_upload_cs_abo_surfaces, -}; - static void brw_upload_cs_image_surfaces(struct brw_context *brw) { /* _NEW_PROGRAM */ - const struct gl_program *cp = brw->compute_program; + const struct gl_program *cp = brw->programs[MESA_SHADER_COMPUTE]; if (cp) { /* BRW_NEW_CS_PROG_DATA, BRW_NEW_IMAGE_UNITS, _NEW_TEXTURE */ @@ -1528,8 +1376,8 @@ const struct brw_tracked_state brw_cs_image_surfaces = { .dirty = { .mesa = _NEW_TEXTURE | _NEW_PROGRAM, .brw = BRW_NEW_BATCH | - BRW_NEW_BLORP | BRW_NEW_CS_PROG_DATA | + BRW_NEW_AUX_STATE | BRW_NEW_IMAGE_UNITS }, .emit = brw_upload_cs_image_surfaces, @@ -1619,7 +1467,7 @@ update_image_surface(struct brw_context *brw, brw_emit_buffer_surface_state( brw, surf_offset, intel_obj->buffer, obj->BufferOffset, format, intel_obj->Base.Size, texel_size, - access != GL_READ_ONLY); + access != GL_READ_ONLY ? RELOC_WRITE : 0); update_buffer_image_param(brw, u, surface_idx, param); @@ -1643,7 +1491,7 @@ update_image_surface(struct brw_context *brw, brw_emit_buffer_surface_state( brw, surf_offset, mt->bo, mt->offset, format, mt->bo->size - mt->offset, 1 /* pitch */, - access != GL_READ_ONLY); + access != GL_READ_ONLY ? RELOC_WRITE : 0); } else { const int surf_index = surf_offset - &brw->wm.base.surf_offset[0]; @@ -1652,11 +1500,9 @@ update_image_surface(struct brw_context *brw, view.base_array_layer, view.array_len)); brw_emit_surface_state(brw, mt, mt->target, view, - ISL_AUX_USAGE_NONE, tex_mocs[brw->gen], + ISL_AUX_USAGE_NONE, surf_offset, surf_index, - I915_GEM_DOMAIN_SAMPLER, - access == GL_READ_ONLY ? 0 : - I915_GEM_DOMAIN_SAMPLER); + access == GL_READ_ONLY ? 0 : RELOC_WRITE); } isl_surf_fill_image_param(&brw->isl_dev, param, &mt->surf, &view); @@ -1664,7 +1510,7 @@ update_image_surface(struct brw_context *brw, } } else { - brw->vtbl.emit_null_surface_state(brw, 1, 1, 1, surf_offset); + emit_null_surface_state(brw, NULL, surf_offset); update_default_image_param(brw, u, surface_idx, param); } } @@ -1686,7 +1532,7 @@ brw_upload_image_surfaces(struct brw_context *brw, update_image_surface(brw, u, prog->sh.ImageAccess[i], surf_idx, &stage_state->surf_offset[surf_idx], - &prog_data->image_param[i]); + &stage_state->image_param[i]); } brw->ctx.NewDriverState |= BRW_NEW_SURFACES; @@ -1702,7 +1548,7 @@ static void brw_upload_wm_image_surfaces(struct brw_context *brw) { /* BRW_NEW_FRAGMENT_PROGRAM */ - const struct gl_program *wm = brw->fragment_program; + const struct gl_program *wm = brw->programs[MESA_SHADER_FRAGMENT]; if (wm) { /* BRW_NEW_FS_PROG_DATA, BRW_NEW_IMAGE_UNITS, _NEW_TEXTURE */ @@ -1715,7 +1561,7 @@ const struct brw_tracked_state brw_wm_image_surfaces = { .dirty = { .mesa = _NEW_TEXTURE, .brw = BRW_NEW_BATCH | - BRW_NEW_BLORP | + BRW_NEW_AUX_STATE | BRW_NEW_FRAGMENT_PROGRAM | BRW_NEW_FS_PROG_DATA | BRW_NEW_IMAGE_UNITS @@ -1723,20 +1569,6 @@ const struct brw_tracked_state brw_wm_image_surfaces = { .emit = brw_upload_wm_image_surfaces, }; -void -gen4_init_vtable_surface_functions(struct brw_context *brw) -{ - brw->vtbl.update_renderbuffer_surface = gen4_update_renderbuffer_surface; - brw->vtbl.emit_null_surface_state = brw_emit_null_surface_state; -} - -void -gen6_init_vtable_surface_functions(struct brw_context *brw) -{ - gen4_init_vtable_surface_functions(brw); - brw->vtbl.update_renderbuffer_surface = brw_update_renderbuffer_surface; -} - static void brw_upload_cs_work_groups_surface(struct brw_context *brw) { @@ -1771,15 +1603,15 @@ brw_upload_cs_work_groups_surface(struct brw_context *brw) brw_emit_buffer_surface_state(brw, surf_offset, bo, bo_offset, ISL_FORMAT_RAW, - 3 * sizeof(GLuint), 1, true); + 3 * sizeof(GLuint), 1, + RELOC_WRITE); brw->ctx.NewDriverState |= BRW_NEW_SURFACES; } } const struct brw_tracked_state brw_cs_work_groups_surface = { .dirty = { - .brw = BRW_NEW_BLORP | - BRW_NEW_CS_PROG_DATA | + .brw = BRW_NEW_CS_PROG_DATA | BRW_NEW_CS_WORK_GROUPS }, .emit = brw_upload_cs_work_groups_surface,