X-Git-Url: https://git.libre-soc.org/?a=blobdiff_plain;ds=sidebyside;f=src%2Fsoc%2Fdecoder%2Fisa%2Fcaller.py;h=77cb681599ccf58078906b7f6dfd9f5bad00e57c;hb=5becf757bae8671aab4712f1ab85f8a92be20037;hp=299b74c0e136a65a0f1a68955e6ccda786e2cf99;hpb=7bcc2eb604806b9b69993974cb0b5519136a7d01;p=soc.git diff --git a/src/soc/decoder/isa/caller.py b/src/soc/decoder/isa/caller.py index 299b74c0..77cb6815 100644 --- a/src/soc/decoder/isa/caller.py +++ b/src/soc/decoder/isa/caller.py @@ -1,3 +1,10 @@ +"""core of the python-based POWER9 simulator + +this is part of a cycle-accurate POWER9 simulator. its primary purpose is +not speed, it is for both learning and educational purposes, as well as +a method of verifying the HDL. +""" + from functools import wraps from soc.decoder.orderedset import OrderedSet from soc.decoder.selectable_int import (FieldSelectableInt, SelectableInt, @@ -19,6 +26,12 @@ special_sprs = { 'VRSAVE': 256} +def swap_order(x, nbytes): + x = x.to_bytes(nbytes, byteorder='little') + x = int.from_bytes(x, byteorder='big', signed=False) + return x + + def create_args(reglist, extra=None): args = OrderedSet() for reg in reglist: @@ -31,19 +44,40 @@ def create_args(reglist, extra=None): class Mem: - def __init__(self, bytes_per_word=8): + def __init__(self, row_bytes=8, initial_mem=None): self.mem = {} - self.bytes_per_word = bytes_per_word - self.word_log2 = math.ceil(math.log2(bytes_per_word)) - - def _get_shifter_mask(self, width, remainder): - shifter = ((self.bytes_per_word - width) - remainder) * \ + self.bytes_per_word = row_bytes + self.word_log2 = math.ceil(math.log2(row_bytes)) + print ("Sim-Mem", initial_mem, self.bytes_per_word, self.word_log2) + if not initial_mem: + return + + # different types of memory data structures recognised (for convenience) + if isinstance(initial_mem, list): + initial_mem = (0, initial_mem) + if isinstance(initial_mem, tuple): + startaddr, mem = initial_mem + initial_mem = {} + for i, val in enumerate(mem): + initial_mem[startaddr + row_bytes*i] = (val, row_bytes) + + for addr, (val, width) in initial_mem.items(): + #val = swap_order(val, width) + self.st(addr, val, width, swap=False) + + def _get_shifter_mask(self, wid, remainder): + shifter = ((self.bytes_per_word - wid) - remainder) * \ 8 # bits per byte - mask = (1 << (width * 8)) - 1 + # XXX https://bugs.libre-soc.org/show_bug.cgi?id=377 + # BE/LE mode? + shifter = remainder * 8 + mask = (1 << (wid * 8)) - 1 + print ("width,rem,shift,mask", wid, remainder, hex(shifter), hex(mask)) return shifter, mask # TODO: Implement ld/st of lesser width - def ld(self, address, width=8): + def ld(self, address, width=8, swap=True): + print("ld from addr 0x{:x} width {:d}".format(address, width)) remainder = address & (self.bytes_per_word - 1) address = address >> self.word_log2 assert remainder & (width - 1) == 0, "Unaligned access unsupported!" @@ -51,30 +85,39 @@ class Mem: val = self.mem[address] else: val = 0 + print("mem @ 0x{:x} rem {:d} : 0x{:x}".format(address, remainder, val)) if width != self.bytes_per_word: shifter, mask = self._get_shifter_mask(width, remainder) + print ("masking", hex(val), hex(mask<>= shifter - print("Read {:x} from addr {:x}".format(val, address)) + if swap: + val = swap_order(val, width) + print("Read 0x{:x} from addr 0x{:x}".format(val, address)) return val - def st(self, address, value, width=8): - remainder = address & (self.bytes_per_word - 1) - address = address >> self.word_log2 + def st(self, addr, v, width=8, swap=True): + staddr = addr + remainder = addr & (self.bytes_per_word - 1) + addr = addr >> self.word_log2 + print("Writing 0x{:x} to ST 0x{:x} memaddr 0x{:x}/{:x}".format(v, + staddr, addr, remainder, swap)) assert remainder & (width - 1) == 0, "Unaligned access unsupported!" - print("Writing {:x} to addr {:x}".format(value, address)) + if swap: + v = swap_order(v, width) if width != self.bytes_per_word: - if address in self.mem: - val = self.mem[address] + if addr in self.mem: + val = self.mem[addr] else: val = 0 shifter, mask = self._get_shifter_mask(width, remainder) val &= ~(mask << shifter) - val |= value << shifter - self.mem[address] = val + val |= v << shifter + self.mem[addr] = val else: - self.mem[address] = value + self.mem[addr] = v + print("mem @ 0x{:x}: 0x{:x}".format(addr, self.mem[addr])) def __call__(self, addr, sz): val = self.ld(addr.value, sz) @@ -162,17 +205,39 @@ class SPR(dict): def __call__(self, ridx): return self[ridx] - - + class ISACaller: # decoder2 - an instance of power_decoder2 # regfile - a list of initial values for the registers - def __init__(self, decoder2, regfile, initial_sprs={}, initial_cr=0): + # initial_{etc} - initial values for SPRs, Condition Register, Mem, MSR + # respect_pc - tracks the program counter. requires initial_insns + def __init__(self, decoder2, regfile, initial_sprs=None, initial_cr=0, + initial_mem=None, initial_msr=0, + initial_insns=None, respect_pc=False): + + self.respect_pc = respect_pc + if initial_sprs is None: + initial_sprs = {} + if initial_mem is None: + initial_mem = {} + if initial_insns is None: + initial_insns = {} + assert self.respect_pc == False, "instructions required to honor pc" + + # "fake program counter" mode (for unit testing) + if not respect_pc: + if isinstance(initial_mem, tuple): + self.fake_pc = initial_mem[0] + else: + self.fake_pc = 0 + self.gpr = GPR(decoder2, regfile) - self.mem = Mem() + self.mem = Mem(row_bytes=8, initial_mem=initial_mem) + self.insns = Mem(row_bytes=4, initial_mem=initial_insns) self.pc = PC() self.spr = SPR(decoder2, initial_sprs) + self.msr = SelectableInt(initial_msr, 64) # underlying reg # TODO, needed here: # FPR (same as GPR except for FP nums) # 4.2.2 p124 FPSCR (definitely "separate" - not in SPR) @@ -200,6 +265,7 @@ class ISACaller: 'NIA': self.pc.NIA, 'CIA': self.pc.CIA, 'CR': self.cr, + 'MSR': self.msr, 'undefined': self.undefined, 'mode_is_64bit': True, 'SO': XER_bits['SO'] @@ -216,6 +282,11 @@ class ISACaller: self.decoder = decoder2.dec self.dec2 = decoder2 + def TRAP(self, trap_addr=0x700): + print ("TRAP: TODO") + # store CIA(+4?) in SRR0, set NIA to 0x700 + # store MSR in SRR1, set MSR to um errr something, have to check spec + def memassign(self, ea, sz, val): self.mem.memassign(ea, sz, val) @@ -239,8 +310,9 @@ class ISACaller: self.namespace['XER'] = self.spr['XER'] self.namespace['CA'] = self.spr['XER'][XER_bits['CA']].value + self.namespace['CA32'] = self.spr['XER'][XER_bits['CA32']].value - def handle_carry_(self, inputs, outputs): + def handle_carry_(self, inputs, outputs, already_done): inv_a = yield self.dec2.e.invert_a if inv_a: inputs[0] = ~inputs[0] @@ -254,14 +326,16 @@ class ISACaller: gts = [(x > output) for x in inputs] print(gts) cy = 1 if any(gts) else 0 - self.spr['XER'][XER_bits['CA']] = cy - + if not (1 & already_done): + self.spr['XER'][XER_bits['CA']] = cy + print ("inputs", inputs) # 32 bit carry gts = [(x[32:64] > output[32:64]) == SelectableInt(1, 1) for x in inputs] cy32 = 1 if any(gts) else 0 - self.spr['XER'][XER_bits['CA32']] = cy32 + if not (2 & already_done): + self.spr['XER'][XER_bits['CA32']] = cy32 def handle_overflow(self, inputs, outputs): inv_a = yield self.dec2.e.invert_a @@ -273,14 +347,24 @@ class ISACaller: imm = yield self.dec2.e.imm_data.data inputs.append(SelectableInt(imm, 64)) assert len(outputs) >= 1 + print ("handle_overflow", inputs, outputs) if len(inputs) >= 2: output = outputs[0] + + # OV (64-bit) input_sgn = [exts(x.value, x.bits) < 0 for x in inputs] output_sgn = exts(output.value, output.bits) < 0 ov = 1 if input_sgn[0] == input_sgn[1] and \ output_sgn != input_sgn[0] else 0 + # OV (32-bit) + input32_sgn = [exts(x.value, 32) < 0 for x in inputs] + output32_sgn = exts(output.value, 32) < 0 + ov32 = 1 if input32_sgn[0] == input32_sgn[1] and \ + output32_sgn != input32_sgn[0] else 0 + self.spr['XER'][XER_bits['OV']] = ov + self.spr['XER'][XER_bits['OV32']] = ov32 so = self.spr['XER'][XER_bits['SO']] so = so | ov self.spr['XER'][XER_bits['SO']] = so @@ -300,7 +384,6 @@ class ISACaller: def set_pc(self, pc_val): self.namespace['NIA'] = SelectableInt(pc_val, 64) self.pc.update(self.namespace) - def call(self, name): # TODO, asmregs is from the spec, e.g. add RT,RA,RB @@ -332,11 +415,23 @@ class ISACaller: results = info.func(self, *inputs) print(results) + # detect if CA/CA32 already in outputs (sra*, basically) + already_done = 0 + if info.write_regs: + output_names = create_args(info.write_regs) + for name in output_names: + if name == 'CA': + already_done |= 1 + if name == 'CA32': + already_done |= 2 + + print ("carry already done?", bin(already_done)) carry_en = yield self.dec2.e.output_carry if carry_en: - yield from self.handle_carry_(inputs, results) - ov_en = yield self.dec2.e.oe - if ov_en: + yield from self.handle_carry_(inputs, results, already_done) + ov_en = yield self.dec2.e.oe.oe + ov_ok = yield self.dec2.e.oe.ok + if ov_en & ov_ok: yield from self.handle_overflow(inputs, results) rc_en = yield self.dec2.e.rc.data if rc_en: @@ -344,12 +439,17 @@ class ISACaller: # any modified return results? if info.write_regs: - output_names = create_args(info.write_regs) for name, output in zip(output_names, results): if isinstance(output, int): output = SelectableInt(output, 256) - if name in info.special_regs: - print('writing special %s' % name, output) + if name in ['CA', 'CA32']: + if carry_en: + print ("writing %s to XER" % name, output) + self.spr['XER'][XER_bits[name]] = output.value + else: + print ("NOT writing %s to XER" % name, output) + elif name in info.special_regs: + print('writing special %s' % name, output, special_sprs) if name in special_sprs: self.spr[name] = output else: @@ -366,7 +466,17 @@ class ISACaller: def inject(): - """ Decorator factory. """ + """Decorator factory. + + this decorator will "inject" variables into the function's namespace, + from the *dictionary* in self.namespace. it therefore becomes possible + to make it look like a whole stack of variables which would otherwise + need "self." inserted in front of them (*and* for those variables to be + added to the instance) "appear" in the function. + + "self.namespace['SI']" for example becomes accessible as just "SI" but + *only* inside the function, when decorated. + """ def variable_injector(func): @wraps(func) def decorator(*args, **kwargs): @@ -375,7 +485,7 @@ def inject(): except AttributeError: func_globals = func.func_globals # Earlier versions. - context = args[0].namespace + context = args[0].namespace # variables to be injected saved_values = func_globals.copy() # Shallow copy of dict. func_globals.update(context) result = func(*args, **kwargs)