X-Git-Url: https://git.libre-soc.org/?a=blobdiff_plain;ds=sidebyside;f=src%2Fsoc%2Flitex%2Fcore.py;h=d391eb700500ede61a3615b897230cfba3a4ecf5;hb=4f0f47658ff6867695736ce8f8a6755927c80fc4;hp=c37f23a8f0c4d45144783da01e6d25699f4a0efe;hpb=c8544d3653c6e49a71eeb6afb2cbdeb3a8bb40c1;p=soc.git

diff --git a/src/soc/litex/core.py b/src/soc/litex/core.py
index c37f23a8..d391eb70 100644
--- a/src/soc/litex/core.py
+++ b/src/soc/litex/core.py
@@ -86,8 +86,8 @@ class LibreSOC(CPU):
             o_ibus__cti   = self.ibus.cti,
             o_ibus__bte   = self.ibus.bte,
             o_ibus__we    = self.ibus.we,
-            #o_ibus__adr   = self.ibus.adr, # 64-bit
-            sigh o_ibus__adr   = Cat(Signal(3), self.ibus.adr), # 64-bit
+            # sigh o_ibus__adr   = self.ibus.adr, # for 32-bit
+            o_ibus__adr   = Cat(Signal(3), self.ibus.adr), # 64-bit
             o_ibus__dat_w = self.ibus.dat_w,
             o_ibus__sel   = self.ibus.sel,
             i_ibus__ack   = self.ibus.ack,