X-Git-Url: https://git.libre-soc.org/?a=blobdiff_plain;ds=sidebyside;f=src%2Fsoc%2Flitex%2Fflorent%2Fls180soc.py;h=f8c71ebbbaf55bf685ed18639a1cb8bfcf66f280;hb=b9821fff0ab14483f5d1373ea7ca106e01436e91;hp=fd6c84b95f20b05bcdf1876c440ae84652d2afd0;hpb=fccc87fecdded95afe472ae7ea1d9b4e9163b831;p=soc.git diff --git a/src/soc/litex/florent/ls180soc.py b/src/soc/litex/florent/ls180soc.py index fd6c84b9..f8c71ebb 100755 --- a/src/soc/litex/florent/ls180soc.py +++ b/src/soc/litex/florent/ls180soc.py @@ -47,7 +47,7 @@ SoCCSRHandler.supported_address_width.append(12) # GPIO Tristate ------------------------------------------------------- # doesn't work properly. #from litex.soc.cores.gpio import GPIOTristate -from litex.soc.interconnect.csr import CSRStorage, CSRStatus +from litex.soc.interconnect.csr import CSRStorage, CSRStatus, CSRField from migen.genlib.cdc import MultiReg # Imports @@ -319,13 +319,16 @@ class LibreSoCSim(SoCCore): self.mem_map["main_ram"] = 0x90000000 self.mem_map["sram"] = 0x00000000 + self.mem_map["sram1"] = 0x00001000 + self.mem_map["sram2"] = 0x00002000 + self.mem_map["sram3"] = 0x00003000 # SoCCore ------------------------------------------------------------- SoCCore.__init__(self, platform, clk_freq=sys_clk_freq, cpu_type = "microwatt", cpu_cls = LibreSoC if cpu == "libresoc" \ else Microwatt, - #bus_data_width = 64, + bus_data_width = 64, csr_address_width = 14, # limit to 0x8000 cpu_variant = variant, csr_data_width = 8, @@ -336,6 +339,7 @@ class LibreSoCSim(SoCCore): sdram_module = sdram_module, sdram_data_width = sdram_data_width, integrated_rom_size = 0, # if ram_fname else 0x10000, + #integrated_sram_size = 0x1000, - problem with yosys ABC integrated_sram_size = 0x200, #integrated_main_ram_init = ram_init, integrated_main_ram_size = 0x00000000 if with_sdram \ @@ -343,6 +347,11 @@ class LibreSoCSim(SoCCore): ) self.platform.name = "ls180" + # add 3 more 4k integrated SRAMs + self.add_ram("sram1", self.mem_map["sram1"], 0x1000) + self.add_ram("sram2", self.mem_map["sram2"], 0x1000) + self.add_ram("sram3", self.mem_map["sram3"], 0x1000) + # SDR SDRAM ---------------------------------------------- if False: # not self.integrated_main_ram_size: self.submodules.sdrphy = sdrphy_cls(platform.request("sdram")) @@ -363,6 +372,15 @@ class LibreSoCSim(SoCCore): self.submodules.crg = CRG(platform.request("sys_clk"), platform.request("sys_rst")) + # PLL/Clock Select + clksel_i = platform.request("sys_clksel_i") + pll18_o = platform.request("sys_pll_18_o") + pll_lck_o = platform.request("sys_pll_lck_o") + + self.comb += self.cpu.clk_sel.eq(clksel_i) # allow clock src select + self.comb += pll18_o.eq(self.cpu.pll_18_o) # "test feed" from the PLL + self.comb += pll_lck_o.eq(self.cpu.pll_lck_o) # PLL lock flag + #ram_init = [] # SDRAM ---------------------------------------------------- @@ -378,7 +396,8 @@ class LibreSoCSim(SoCCore): clk_freq = sdram_clk_freq) #sdrphy_cls = HalfRateGENSDRPHY sdrphy_cls = GENSDRPHY - self.submodules.sdrphy = sdrphy_cls(platform.request("sdram")) + sdram_pads = self.cpu.cpupads['sdr'] + self.submodules.sdrphy = sdrphy_cls(sdram_pads) #self.submodules.sdrphy = sdrphy_cls(sdram_module, # phy_settings, # init=ram_init @@ -402,7 +421,7 @@ class LibreSoCSim(SoCCore): # SDRAM clock sys_clk = ClockSignal() - sdr_clk = platform.request("sdram_clock") + sdr_clk = self.cpu.cpupads['sdram_clock'] #self.specials += DDROutput(1, 0, , sdram_clk) self.specials += SDROutput(clk=sys_clk, i=sys_clk, o=sdr_clk) @@ -415,11 +434,6 @@ class LibreSoCSim(SoCCore): self.submodules.uart = ResetInserter()(uart.UART(self.uart_phy, tx_fifo_depth = 16, rx_fifo_depth = 16)) - # "real" pads connect to C4M JTAG iopad - uart_pads = platform.request(uart_name) # "real" (actual) pin - uart_io_pads = self.cpu.iopads['uart'] # C4M JTAG pads - self.comb += uart_pads.tx.eq(uart_io_pads.tx) - self.comb += uart_io_pads.rx.eq(uart_pads.rx) self.csr.add("uart_phy", use_loc_if_exists=True) self.csr.add("uart", use_loc_if_exists=True) @@ -430,23 +444,28 @@ class LibreSoCSim(SoCCore): self.submodules.gpio = GPIOTristateASIC(gpio_core_pads) self.add_csr("gpio") - gpio_pads = platform.request("gpio") # "real" (actual) pins - gpio_io_pads = self.cpu.iopads['gpio'] # C4M JTAG pads - self.comb += gpio_io_pads.i.eq(gpio_pads.i) - self.comb += gpio_pads.o.eq(gpio_io_pads.o) - self.comb += gpio_pads.oe.eq(gpio_io_pads.oe) - # SPI Master - self.submodules.spi_master = SPIMaster( - pads = platform.request("spi_master"), + print ("cpupadkeys", self.cpu.cpupads.keys()) + self.submodules.spimaster = SPIMaster( + pads = self.cpu.cpupads['mspi1'], data_width = 8, sys_clk_freq = sys_clk_freq, spi_clk_freq = 8e6, ) - self.add_csr("spi_master") + self.add_csr("spimaster") + + # SPI SDCard (1 wide) + spi_clk_freq = 400e3 + pads = self.cpu.cpupads['mspi0'] + spisdcard = SPIMaster(pads, 8, self.sys_clk_freq, spi_clk_freq) + spisdcard.add_clk_divider() + setattr(self.submodules, 'spisdcard', spisdcard) + self.add_csr('spisdcard') # EINTs - very simple, wire up top 3 bits to ls180 "eint" pins - self.comb += self.cpu.interrupt[12:16].eq(platform.request("eint")) + eintpads = self.cpu.cpupads['eint'] + print ("eintpads", eintpads) + self.comb += self.cpu.interrupt[12:16].eq(eintpads) # JTAG jtagpads = platform.request("jtag") @@ -466,20 +485,21 @@ class LibreSoCSim(SoCCore): self.sync += self.dummy[i].eq(self.nc[i] | self.cpu.interrupt[0]) # PWM + pwmpads = self.cpu.cpupads['pwm'] for i in range(2): name = "pwm%d" % i - setattr(self.submodules, name, PWM(platform.request("pwm", i))) + setattr(self.submodules, name, PWM(pwmpads[i])) self.add_csr(name) - if False: # TODO: convert to _i _o _oe - # I2C Master - self.submodules.i2c = I2CMaster(platform.request("i2c")) - self.add_csr("i2c") + # I2C Master + i2c_core_pads = self.cpu.cpupads['mtwi'] + self.submodules.i2c = I2CMaster(i2c_core_pads) + self.add_csr("i2c") # SDCard ----------------------------------------------------- # Emulator / Pads - sdcard_pads = self.platform.request("sdcard") + sdcard_pads = self.cpu.cpupads['sd0'] # Core self.submodules.sdphy = SDPHY(sdcard_pads, @@ -512,6 +532,8 @@ class LibreSoCSim(SoCCore): if not debug: return + jtag_en = ('jtag' in variant) or variant == 'ls180' + # setup running of DMI FSM dmi_addr = Signal(4) dmi_din = Signal(64) @@ -795,7 +817,6 @@ def main(): if args.platform == 'ls180': soc = LibreSoCSim(cpu=args.cpu, debug=args.debug, platform=args.platform) - soc.add_spi_sdcard() builder = Builder(soc, compile_gateware = True) builder.build(run = True) os.chdir("../")