X-Git-Url: https://git.libre-soc.org/?a=blobdiff_plain;f=.gitmodules;h=2336869ef45b9cf20dacb5852ca3a22d201dcc06;hb=8bfb845f9ccc3111d7f37969f072435428a5e005;hp=26af8537e81648def9d1cdbb5059ba3b7fc4f5cd;hpb=f60da4a5dcb00366f45e8423ab42d4bfa38051eb;p=litex.git

diff --git a/.gitmodules b/.gitmodules
index 26af8537..2336869e 100644
--- a/.gitmodules
+++ b/.gitmodules
@@ -6,13 +6,25 @@
 	url = https://github.com/openrisc/mor1kx.git
 [submodule "litex/soc/software/compiler_rt"]
 	path = litex/soc/software/compiler_rt
-	url = http://llvm.org/git/compiler-rt.git
+	url = https://git.llvm.org/git/compiler-rt
 [submodule "litex/soc/cores/cpu/picorv32/verilog"]
 	path = litex/soc/cores/cpu/picorv32/verilog
 	url = https://github.com/cliffordwolf/picorv32
 [submodule "litex/build/sim/core/modules/ethernet/tapcfg"]
 	path = litex/build/sim/core/modules/ethernet/tapcfg
-	url = https://github.com/nizox/tapcfg
+	url = https://github.com/enjoy-digital/tapcfg
 [submodule "litex/soc/cores/cpu/vexriscv/verilog"]
 	path = litex/soc/cores/cpu/vexriscv/verilog
-	url = https://github.com/m-labs/VexRiscv-verilog.git
+	url = https://github.com/enjoy-digital/VexRiscv-verilog.git
+[submodule "litex/soc/cores/cpu/minerva/verilog"]
+	path = litex/soc/cores/cpu/minerva/verilog
+	url = https://github.com/lambdaconcept/minerva
+[submodule "litex/soc/cores/cpu/rocket/verilog"]
+	path = litex/soc/cores/cpu/rocket/verilog
+	url = https://github.com/enjoy-digital/rocket-litex-verilog
+[submodule "litex/soc/cores/cpu/microwatt/sources"]
+	path = litex/soc/cores/cpu/microwatt/sources
+	url = https://github.com/antonblanchard/microwatt
+[submodule "litex/soc/cores/cpu/blackparrot/pre-alpha-release"]
+	path = litex/soc/cores/cpu/blackparrot/pre-alpha-release
+	url = https://github.com/enjoy-digital/black-parrot.git