X-Git-Url: https://git.libre-soc.org/?a=blobdiff_plain;f=.gitmodules;h=26af8537e81648def9d1cdbb5059ba3b7fc4f5cd;hb=eda1a83ea991958ae98ea0e28f93d6be34271b5b;hp=07ef9c74a2611b6b894040cfdd0256fe7e49c312;hpb=9aa474c6f0163cd010d1600ffb4dd21c97d99ae3;p=litex.git

diff --git a/.gitmodules b/.gitmodules
index 07ef9c74..26af8537 100644
--- a/.gitmodules
+++ b/.gitmodules
@@ -1,3 +1,18 @@
-[submodule "verilog/lm32/submodule"]
-	path = verilog/lm32/submodule
+[submodule "litex/soc/cores/cpu/lm32/verilog/submodule"]
+	path = litex/soc/cores/cpu/lm32/verilog/submodule
 	url = https://github.com/m-labs/lm32.git
+[submodule "litex/soc/cores/cpu/mor1kx/verilog"]
+	path = litex/soc/cores/cpu/mor1kx/verilog
+	url = https://github.com/openrisc/mor1kx.git
+[submodule "litex/soc/software/compiler_rt"]
+	path = litex/soc/software/compiler_rt
+	url = http://llvm.org/git/compiler-rt.git
+[submodule "litex/soc/cores/cpu/picorv32/verilog"]
+	path = litex/soc/cores/cpu/picorv32/verilog
+	url = https://github.com/cliffordwolf/picorv32
+[submodule "litex/build/sim/core/modules/ethernet/tapcfg"]
+	path = litex/build/sim/core/modules/ethernet/tapcfg
+	url = https://github.com/nizox/tapcfg
+[submodule "litex/soc/cores/cpu/vexriscv/verilog"]
+	path = litex/soc/cores/cpu/vexriscv/verilog
+	url = https://github.com/m-labs/VexRiscv-verilog.git