X-Git-Url: https://git.libre-soc.org/?a=blobdiff_plain;f=3d_gpu%2Flayouts%2Fcoriolis2_180nm.mdwn;h=c6f67ec9af54b7ce3679a69076db54ca79f5850a;hb=dfcf992cb61bf0de42700ba361d934659ab06ca1;hp=068af11b92dcb59735df1ee9498048d97169a6af;hpb=caeb71d0bd35f2a3c0867a569162cbc1004f3aa7;p=libreriscv.git

diff --git a/3d_gpu/layouts/coriolis2_180nm.mdwn b/3d_gpu/layouts/coriolis2_180nm.mdwn
index 068af11b9..c6f67ec9a 100644
--- a/3d_gpu/layouts/coriolis2_180nm.mdwn
+++ b/3d_gpu/layouts/coriolis2_180nm.mdwn
@@ -1,8 +1,9 @@
 # Coriolis2 180nm layout
 
-* <http://bugs.libre-riscv.org/show_bug.cgi?id=138> - toplevel
-* <http://bugs.libre-riscv.org/show_bug.cgi?id=199> - main layout
-* <https://ftp.libre-soc.org/course_18oct2021/>
+* <http://bugs.libre-soc.org/show_bug.cgi?id=138> - toplevel
+* <http://bugs.libre-soc.org/show_bug.cgi?id=199> - main layout
+* <http://bugs.libre-soc.org/show_bug.cgi?id=205> - this page
+* <https://ftp.libre-soc.org/course_18oct2021>
 * [[180nm_Oct2020]]
 
 # Simple floorplan
@@ -11,7 +12,7 @@
 
 ## Register files
 
-There are 5 register files: SPR, INT, CR, XER and FAST.
+There are 6 register files: STATE, SPR, INT, CR, XER and FAST.
 
 Access to each of the ports is managed via a "Priority Picker" - an
 unary-in but one-hot unary-out picker - which allows one and only one
@@ -53,6 +54,8 @@ with a proper connection to the Memory Bus (wishbone).
 
 # IO Ring and JTAG
 
+[[!img 180nm_Oct2020/ls180.svg size="500x" ]]
+
 The IO Ring is autogenerated from the same pinmux program
 that created the [[180nm_Oct2020/pinouts]] and the SVG
 image. The image was used by Greatek for packaging as well as
@@ -70,9 +73,18 @@ to ensure complete consistency across
 * IO Ring
 * JTAG Boundary Scan
 
-JTAG 
+JTAG also contains a Wishbone Master for direct access to Memory
+and also a DMI Interface for controlling the core.  In simulations
+a JTAG client was implemented both in nmigen HDL as well as
+verilator.  The exact same openocd scripts or direct
+JTAG connectivity using jtagremote can then be used on:
+
+* nmigen HDL simulations
+* verilator simulations
+* [[HDL_workflow/ECP5_FPGA]]
+* the actual ls180 ASIC
 
-[[!img 180nm_Oct2020/ls180.svg size="400x" ]]
+<img src="https://ftp.libre-soc.org/course_18oct2021/drawing-4.svg" width=500 />
 
 # Building
 
@@ -86,3 +98,24 @@ There are several talks online now.
 
 * [[conferences/fosdem2022]]
 * <https://m.youtube.com/playlist?list=PLBtNqZjUZB80uByfZVm0gGYEtmTG0mZzm>
+
+Jean-Paul Chaput of LIP6 carried out several improvements to coriolis2
+in order for it to cope with an 800,000 transistor 30 mm^2 180nm layout.
+These included:
+
+* automatic antennae diodes (needed for stopping ESD),
+* clock tree improvements
+* Dual Power rings (Core, IO)
+* Automatic buffer insertion (clock tree synchronised)
+* High fanout buffers (1 to 128) and repeater buffers
+
+Overall it was a significant amount of work and it is entirely
+automated `RTL2GDS`, no manual intervention required.
+
+<img src="https://ftp.libre-soc.org/course_18oct2021/drawing-2.svg" width=500 />
+
+coriolis2 converts verilog to BLIF using yosys and the Cell Library, then converts
+BLIF into a VHDL subset.  This subset is extremely simple, comprising
+links (netlists) to cells and nothing more. It can be extracted and
+converted to actual VHDL and substituted successfully into verilator,
+ghdl or icarus simulations using cocotb (caveat: the files are enormous).