X-Git-Url: https://git.libre-soc.org/?a=blobdiff_plain;f=3d_gpu.mdwn;h=018354543d98c2c174780fbe7c3349ad7af21ded;hb=629cbbfe2773bcb9fe9b1f2aa809f14efa240d7d;hp=8bdb992820cfc734ab89dde623e5c450ddcd386b;hpb=86eac212ed03585f82990136e9143f7fede884d7;p=libreriscv.git diff --git a/3d_gpu.mdwn b/3d_gpu.mdwn index 8bdb99282..018354543 100644 --- a/3d_gpu.mdwn +++ b/3d_gpu.mdwn @@ -1,31 +1,61 @@ -# RISC-V 3D GPU / CPU / VPU +# Hybrid 3D GPU / CPU / VPU + +Creating a trustworthy processor for the world. + +Our [[3d_gpu/business_objectives]] Note: this is a **hybrid** CPU, VPU and GPU. It is not, as many news articles -are implying, a "dedicated exclusive GPU". The option exists to **create** -a stand-alone GPU product. It is being *designed* to be a **complete** -all-in-one processor (System-on-a-Chip). - -We seek investors, sponsors, engineers and potential customers, who are -interested in the creation and use of an entirely libre low-power mobile -class system-on-a-chip. Comparative benchmark performance, pincount and -price is the Allwinner A64, except that the power budget target is 2.5 watts -in a 16x16mm 320 to 360 pin 0.8mm FBGA package. - -See: - -* [[shakti/m_class/libre_3d_gpu]] -* [[discussion]] -* Founding [[charter]] -* Mailing list -* Crowdsupply page -* Wiki -* Git repositories -* Bugtracker -* Kazan Vulkan Driver (including 3D engine) -* [NLNet 2019 Milestones](http://bugs.libre-riscv.org/buglist.cgi?columnlist=assigned_to%2Cbug_status%2Cresolution%2Cshort_desc%2Ccf_budget&f1=cf_nlnet_milestone&o1=equals&query_format=advanced&resolution=---&v1=NLnet.2019.02) - -Progress: +are implying, a "dedicated exclusive GPU". The option exists to *create* +a stand-alone GPU product (contact us if this is a product that you want). +Our primary goal is to design a **complete** all-in-one processor +(System-on-a-Chip) that happens to include libre-licensed VPU and GPU +accelerated instructions as part of the actual - main - CPU itself. + +We seek investors, sponsors (whose contributions thanks to NLNet may be +tax-deductible), engineers and potential customers, who are +interested, as a first product, in the creation and use of an entirely +libre low-power mobile class system-on-a-chip. Comparative benchmark +performance, pincount and price is the Allwinner A64, except that the +power budget target is 2.5 watts in a 16x16mm 320 to 360 pin 0.8mm +FBGA package. Instead of single-issue higher clock rate, the design is +multi-issue, aiming for around 800mhz. + +The lower pincount, lower power, and higher BGA pitch is all to reduce +the cost of product development when it comes to PCB design and layout: + +* Above 4 watts requires metal packages, greater attention to thermal + management in the PCB design and layout, and much pricier PMICs. +* 0.6mm pitch BGA and below requires much more expensive PCB manufacturing + equipment and more costly PCBA techniques. +* Above 600 pins begins to reduce production yields as well as increase + the cost of testing and packaging. + +We can look at larger higher-power ASICs either later or, if funding +is made available, immediately. + +Recent applications to NLNet (Oct 2019) are for a test chip in 180nm, +64 bit, single core dual issue, around 300 to 350mhz. This will provide +the confidence to go to higher geometries, as well as be a commercially +viable embedded product in its own right. Tapeout deadline is Oct 2020. +See [[3d_gpu/articles]] online. + +# Progress: + +* Mar 2020: Coriolis2 Layout experiments successful. 6600 Memory Architecture + exploration started. OpenPOWER ISA decoder started. Two new people: + Alain and Jock. +* Feb 2020: OpenPower Foundation EULA released. Coriolis2 Layout experimentation begun. Dynamic Partitioned SIMD ALU created. +* Jan 2020: New team members, Yehowshua and Michael. Last-minute attendance of FOSDEM2020 +* Dec 2019: Second round NLNet questions answered. External Review completed. 6 NLNet proposals accepted (EUR 200,000+) +* Nov 2019: Alternative FP library to Berkeley softfloat developed. NLNet first round questions answered. +* Oct 2019: 3D Standards continued. POWER ISA considered. Open 3D Alliance begins. NLNet funding applications submitted. +* Sep 2019: 3D Standards continued. Additional NLNet Funding proposals discussed. +* Aug 2019: Development of "Transcendentals" (SIN/COS/ATAN2) Specifications +* Jul 2019: Sponsorship from Purism received. IEEE754 FP Mul, Add, DIV, + FCLASS and FCVT pipelines completed. +* Jun 2019: IEEE754 FP Mul, Add, and FSM "DIV" completed. +* May 2019: 6600-style scoreboard started * Apr 2019: NLnet funding approved by independent review committee * Mar 2019: NLnet funding application first and second phase passed * Mar 2019: First successful nmigen pipeline milestone achieved with IEEE754 FADD @@ -38,54 +68,11 @@ Progress: * Sep 2018: Crowdsupply pre-launch page up (for updates) * Dec 2018: preliminary floorplan and architecture designed (comp.arch) -# News Articles - -* -* -* -* -* -* -* -* -* -* -* -* -* -* - -# Information Resources and Tutorials - -* -* -* -* -* -* -* -* -* -* -* - -* -* -* -* -* -* -* -* -* -* -* -* -* -* - -# Analog Simulation - -* -* -* -* + +# Evaluations + +* [[openpower]] + +# Drivers + +* [[3d_gpu/opencl]]