X-Git-Url: https://git.libre-soc.org/?a=blobdiff_plain;f=3d_gpu.mdwn;h=1defb461d1283bb35645f42966f9f18c7a1d3ef2;hb=ffc6f3814e7d134949c3dc061ded3405a3d5eb45;hp=89a432b62622cb3bddcf6bb14547eed9dd7ed0ef;hpb=8887102b43cee76dfab68ff78707d23e403d04f6;p=libreriscv.git
diff --git a/3d_gpu.mdwn b/3d_gpu.mdwn
index 89a432b62..1defb461d 100644
--- a/3d_gpu.mdwn
+++ b/3d_gpu.mdwn
@@ -1,14 +1,23 @@
-# RISC-V 3D GPU / CPU / VPU
+See architectural details [here](./architecture), [[gaddie]] pitch and [[business_plan]]
+
+# Hybrid 3D GPU / CPU / VPU
+
+Creating a trustworthy processor for the world.
+
+Our [[3d_gpu/business_objectives]]
Note: this is a **hybrid** CPU, VPU and GPU. It is not, as many news articles
-are implying, a "dedicated exclusive GPU". The option exists to **create**
+are implying, a "dedicated exclusive GPU". The option exists to *create*
a stand-alone GPU product (contact us if this is a product that you want).
Our primary goal is to design a **complete** all-in-one processor
-(System-on-a-Chip) that happens to include a libre-licensed VPU and GPU.
+(System-on-a-Chip) that happens to include libre-licensed VPU and GPU
+accelerated instructions as part of the actual - main - CPU itself. This greatly simplifies driver development, applications integration and debugging, reducing costs and time to market in the process.
-We seek investors, sponsors, engineers and potential customers, who are
+We seek investors, sponsors (whose contributions thanks to NLNet may be
+tax-deductible), engineers and potential customers, who are
interested, as a first product, in the creation and use of an entirely
-libre low-power mobile class system-on-a-chip. Comparative benchmark
+libre low-power mobile class system-on-a-chip
+[[shakti/m_class/]]. Comparative benchmark
performance, pincount and price is the Allwinner A64, except that the
power budget target is 2.5 watts in a 16x16mm 320 to 360 pin 0.8mm
FBGA package. Instead of single-issue higher clock rate, the design is
@@ -27,26 +36,40 @@ the cost of product development when it comes to PCB design and layout:
We can look at larger higher-power ASICs either later or, if funding
is made available, immediately.
-Recent applications to NLNet (Oct 2019) are for a test chip in 180nm, 64 bit, single core dual issue, around 300 to 350mhz. This will provide the confidence to go to higher geometries, as well as be a commercially viable embedded product in its own right.
-
-See:
-
-* [[shakti/m_class/libre_3d_gpu]]
-* [[discussion]]
-* [[resources]]
-* Founding [[charter]]
-* Mailing list
-* Crowdsupply page
-* Wiki
-* Git repositories
-* Bugtracker
-* Kazan Vulkan Driver (including 3D engine)
-* [NLNet 2019 Milestones](http://bugs.libre-riscv.org/buglist.cgi?columnlist=assigned_to%2Cbug_status%2Cresolution%2Cshort_desc%2Ccf_budget&f1=cf_nlnet_milestone&o1=equals&query_format=advanced&resolution=---&v1=NLnet.2019.02)
-* NLNet Project Page
-* [[nlnet_proposals]]
-
-Progress:
-
+Recent applications to NLNet (Oct 2019) are for a test chip in 180nm,
+64 bit, single core dual issue, around 300 to 350mhz. This will provide
+the confidence to go to higher geometries, as well as be a commercially
+viable embedded product in its own right. Tapeout deadline is Oct 2020.
+
+See [[3d_gpu/articles]] online.
+
+# Progress:
+
+* Dec 2021 first MMU unit tests pass, running microwatt mmu.bin.
+ Shows MMU and L1 D/I-Caches as functional in simulation.
+* Apr 2021 cocotb simulation of 180nm ASIC implemented. JTAG TAP
+ confirmed functional on ECP5 and simulation. FreePDK-c4m45
+ created by
+* Mar 2021 first SVP64 OpenPOWER augmented Cray-style instructions executed.
+ NGI POINTER EUR 200,000 grant submitted.
+* Feb 2021 FOSDEM2021, Simple-V SVP64 implementation starts in
+ simulator and Test Issuer
+* Jan 2021 FOSDEM2021 talks confirmed, NLnet crypto-primitives proposal
+ submitted, budget agreed for basic binutils and gcc SVP64 support
+* Dec 2020 work on [[openpower/sv/svp64]] started
+* Nov 2020 dry-run 180nm GDSII sent to IMEC
+* Oct 2020 [[180nm_Oct2020/ls180/]] pinouts decided, code-freeze initiated
+ for 180nm test ASIC, GDSII deadline set of Dec 2nd.
+* Sep 2020: [first boot](https://youtu.be/72QmWro9BSE) of Litex BIOS on a Versa ECP5 at 55mhz. DDR3 RAM initialisation successful. 180nm ASIC pinouts started [[180nm_Oct2020/ls180]]
+* Aug 2020: [first boot](https://libre-soc.org/3d_gpu/libresoc_litex_bios_first_execution_2020-08-06_16-15.png) of litex BIOS in verilator simulation
+* Jul 2020: first ppc64le "hello world" binary executed. 80,000 gate coriolis2 auto-layout completed with 99.98% routing. Wishbone MoU signed making available access to an additional EUR 50,000 donations from NLNet. XDC2020 and OpenPOWER conference submissions entered.
+* Jun 2020: core unit tests and pipeline formal correctness proofs in place.
+* May 2020: first integer pipelines (ALU, Logical, Branch, Trap, SPR, ShiftRot, Mul, Div) and register files (XER, CR, INT, FAST, SPR) started.
+* Mar 2020: Coriolis2 Layout experiments successful. 6600 Memory Architecture
+ exploration started. OpenPOWER ISA decoder started. Two new people:
+ Alain and Jock.
+* Feb 2020: OpenPower Foundation EULA released. Coriolis2 Layout experimentation begun. Dynamic Partitioned SIMD ALU created.
+* Jan 2020: New team members, Yehowshua and Michael. Last-minute attendance of FOSDEM2020
* Dec 2019: Second round NLNet questions answered. External Review completed. 6 NLNet proposals accepted (EUR 200,000+)
* Nov 2019: Alternative FP library to Berkeley softfloat developed. NLNet first round questions answered.
* Oct 2019: 3D Standards continued. POWER ISA considered. Open 3D Alliance begins. NLNet funding applications submitted.
@@ -68,70 +91,12 @@ Progress:
* Sep 2018: Crowdsupply pre-launch page up (for updates)
* Dec 2018: preliminary floorplan and architecture designed (comp.arch)
-# News Articles
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-# Information Resources and Tutorials
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-* Fundamentals of Modern VLSI Devices
-
-# Analog Simulation
-
-*
-*
-*
-*
# Evaluations
-*[[openpower]]
+* [[openpower]]
+
+# Drivers
+
+* [[3d_gpu/opencl]]
+* [[3d_gpu/mesa]]