X-Git-Url: https://git.libre-soc.org/?a=blobdiff_plain;f=3d_gpu.mdwn;h=3a87aee52f86bf6bd58a167d2b794818b3938d73;hb=052cbb0ead545ba5b901ce4a2cfde90a7e5cce63;hp=1e18c36d66ad566097f6c6289c6b992e26475501;hpb=950845c7c05f88d5c3e59726620248c7b459ac11;p=libreriscv.git

diff --git a/3d_gpu.mdwn b/3d_gpu.mdwn
index 1e18c36d6..3a87aee52 100644
--- a/3d_gpu.mdwn
+++ b/3d_gpu.mdwn
@@ -44,7 +44,8 @@ See [[3d_gpu/articles]] online.
 
 # Progress:
 
-* Aug 2020: [[first boot]](https://libre-soc.org/3d_gpu/libresoc_litex_bios_first_execution_2020-08-06_16-15.png) of litex BIOS in verilator simulation
+* Sep 2020: [first boot](https://youtu.be/72QmWro9BSE) of Litex BIOS on a Versa ECP5 at 55mhz.  DDR3 RAM initialisation successful.
+* Aug 2020: [first boot](https://libre-soc.org/3d_gpu/libresoc_litex_bios_first_execution_2020-08-06_16-15.png) of litex BIOS in verilator simulation
 * Jul 2020: first ppc64le "hello world" binary executed.  80,000 gate coriolis2 auto-layout completed with 99.98% routing. Wishbone MoU signed making available access to an additional EUR 50,000 donations from NLNet. XDC2020 and OpenPOWER conference submissions entered.
 * Jun 2020: core unit tests and pipeline formal correctness proofs in place.
 * May 2020: first integer pipelines (ALU, Logical, Branch, Trap, SPR, ShiftRot, Mul, Div) and register files (XER, CR, INT, FAST, SPR) started.
@@ -82,3 +83,4 @@ See [[3d_gpu/articles]] online.
 # Drivers
 
 * [[3d_gpu/opencl]]
+* [[3d_gpu/mesa]]