X-Git-Url: https://git.libre-soc.org/?a=blobdiff_plain;f=3d_gpu.mdwn;h=3a87aee52f86bf6bd58a167d2b794818b3938d73;hb=052cbb0ead545ba5b901ce4a2cfde90a7e5cce63;hp=965ffd22c5edb86ca1cdcf7cfc81b7b1064776ef;hpb=2fa0d19106458ff807ccdbe1da783091cbd833f3;p=libreriscv.git diff --git a/3d_gpu.mdwn b/3d_gpu.mdwn index 965ffd22c..3a87aee52 100644 --- a/3d_gpu.mdwn +++ b/3d_gpu.mdwn @@ -1,12 +1,20 @@ -# RISC-V 3D GPU / CPU / VPU +See architectural details [here](./architecture) + +# Hybrid 3D GPU / CPU / VPU + +Creating a trustworthy processor for the world. + +Our [[3d_gpu/business_objectives]] Note: this is a **hybrid** CPU, VPU and GPU. It is not, as many news articles -are implying, a "dedicated exclusive GPU". The option exists to **create** +are implying, a "dedicated exclusive GPU". The option exists to *create* a stand-alone GPU product (contact us if this is a product that you want). Our primary goal is to design a **complete** all-in-one processor -(System-on-a-Chip) that happens to include a libre-licensed VPU and GPU. +(System-on-a-Chip) that happens to include libre-licensed VPU and GPU +accelerated instructions as part of the actual - main - CPU itself. This greatly simplifies driver development, applications integration and debugging, reducing costs and time to market in the process. -We seek investors, sponsors, engineers and potential customers, who are +We seek investors, sponsors (whose contributions thanks to NLNet may be +tax-deductible), engineers and potential customers, who are interested, as a first product, in the creation and use of an entirely libre low-power mobile class system-on-a-chip. Comparative benchmark performance, pincount and price is the Allwinner A64, except that the @@ -27,43 +35,25 @@ the cost of product development when it comes to PCB design and layout: We can look at larger higher-power ASICs either later or, if funding is made available, immediately. -Recent applications to NLNet (Oct 2019) are for a test chip in 180nm, 64 bit, single core dual issue, around 300 to 350mhz. This will provide the confidence to go to higher geometries, as well as be a commercially viable embedded product in its own right. - -# Business Objectives - -* the project shall be a hybrid CPU-GPU because if it is not, the - complexity involved in developing a split shared-memory CPU-GPU both - at a hardware and a software level will be so costly it will jeapordise - the project. -* the project shall be commercial and mass-volume (100 million units - and above) -* the project shall be entirely transparent so that end-users will be - able to trust it -* the source code shall be available at all times for all components - for BUSINESS reasons, making development and use of SDKs dead simple - and aiding and assisting developers AND BUSINESSES in debugging and thus - hugely saving them money. - -# Links: - -* [[shakti/m_class/libre_3d_gpu]] -* [[discussion]] -* [[resources]] -* [[overview]] -* [[3d_gpu/funding]] -* Founding [[charter]] -* Mailing list -* Crowdsupply page -* Wiki -* Git repositories -* Bugtracker -* Kazan Vulkan Driver (including 3D engine) -* [NLNet 2019 Milestones](http://bugs.libre-riscv.org/buglist.cgi?columnlist=assigned_to%2Cbug_status%2Cresolution%2Cshort_desc%2Ccf_budget&f1=cf_nlnet_milestone&o1=equals&query_format=advanced&resolution=---&v1=NLnet.2019.02) -* NLNet Project Page -* [[nlnet_proposals]] +Recent applications to NLNet (Oct 2019) are for a test chip in 180nm, +64 bit, single core dual issue, around 300 to 350mhz. This will provide +the confidence to go to higher geometries, as well as be a commercially +viable embedded product in its own right. Tapeout deadline is Oct 2020. + +See [[3d_gpu/articles]] online. # Progress: +* Sep 2020: [first boot](https://youtu.be/72QmWro9BSE) of Litex BIOS on a Versa ECP5 at 55mhz. DDR3 RAM initialisation successful. +* Aug 2020: [first boot](https://libre-soc.org/3d_gpu/libresoc_litex_bios_first_execution_2020-08-06_16-15.png) of litex BIOS in verilator simulation +* Jul 2020: first ppc64le "hello world" binary executed. 80,000 gate coriolis2 auto-layout completed with 99.98% routing. Wishbone MoU signed making available access to an additional EUR 50,000 donations from NLNet. XDC2020 and OpenPOWER conference submissions entered. +* Jun 2020: core unit tests and pipeline formal correctness proofs in place. +* May 2020: first integer pipelines (ALU, Logical, Branch, Trap, SPR, ShiftRot, Mul, Div) and register files (XER, CR, INT, FAST, SPR) started. +* Mar 2020: Coriolis2 Layout experiments successful. 6600 Memory Architecture + exploration started. OpenPOWER ISA decoder started. Two new people: + Alain and Jock. +* Feb 2020: OpenPower Foundation EULA released. Coriolis2 Layout experimentation begun. Dynamic Partitioned SIMD ALU created. +* Jan 2020: New team members, Yehowshua and Michael. Last-minute attendance of FOSDEM2020 * Dec 2019: Second round NLNet questions answered. External Review completed. 6 NLNet proposals accepted (EUR 200,000+) * Nov 2019: Alternative FP library to Berkeley softfloat developed. NLNet first round questions answered. * Oct 2019: 3D Standards continued. POWER ISA considered. Open 3D Alliance begins. NLNet funding applications submitted. @@ -85,71 +75,12 @@ Recent applications to NLNet (Oct 2019) are for a test chip in 180nm, 64 bit, si * Sep 2018: Crowdsupply pre-launch page up (for updates) * Dec 2018: preliminary floorplan and architecture designed (comp.arch) -# News Articles - -* -* -* -* -* -* -* -* -* -* -* -* -* -* -* -* -* -* -* -* -* -* -* -* - -# Information Resources and Tutorials - -* -* -* -* -* -* -* -* -* -* -* - -* -* -* -* -* -* -* -* -* -* -* -* -* -* -* -* -* Fundamentals of Modern VLSI Devices - -# Analog Simulation - -* -* -* -* # Evaluations -*[[openpower]] +* [[openpower]] + +# Drivers + +* [[3d_gpu/opencl]] +* [[3d_gpu/mesa]]