X-Git-Url: https://git.libre-soc.org/?a=blobdiff_plain;f=3d_gpu.mdwn;h=3c326840f13d51cfabece14b194516c8fd778ceb;hb=2c2ef9f0cec823edc917636c695c440e7345ca8a;hp=8d3370bde7a9f16ea1e699a0cf09df42a94c1e86;hpb=7c3c8b7a25c12a7acf9d85128eb6fbb519b7704d;p=libreriscv.git
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+++ b/3d_gpu.mdwn
@@ -1,25 +1,82 @@
# RISC-V 3D GPU / CPU / VPU
+Creating a trustworthy processor for the world.
+
Note: this is a **hybrid** CPU, VPU and GPU. It is not, as many news articles
-are implying, a "dedicated exclusive GPU". The option exists to **create**
-a stand-alone GPU product. It is being *designed* to be a **complete**
-all-in-one processor (System-on-a-Chip).
+are implying, a "dedicated exclusive GPU". The option exists to *create*
+a stand-alone GPU product (contact us if this is a product that you want).
+Our primary goal is to design a **complete** all-in-one processor
+(System-on-a-Chip) that happens to include libre-licensed VPU and GPU
+accelerated instructions as part of the actual - main - CPU itself.
+
+We seek investors, sponsors (whose contributions thanks to NLNet may be
+tax-deductible), engineers and potential customers, who are
+interested, as a first product, in the creation and use of an entirely
+libre low-power mobile class system-on-a-chip. Comparative benchmark
+performance, pincount and price is the Allwinner A64, except that the
+power budget target is 2.5 watts in a 16x16mm 320 to 360 pin 0.8mm
+FBGA package. Instead of single-issue higher clock rate, the design is
+multi-issue, aiming for around 800mhz.
+
+The lower pincount, lower power, and higher BGA pitch is all to reduce
+the cost of product development when it comes to PCB design and layout:
+
+* Above 4 watts requires metal packages, greater attention to thermal
+ management in the PCB design and layout, and much pricier PMICs.
+* 0.6mm pitch BGA and below requires much more expensive PCB manufacturing
+ equipment and more costly PCBA techniques.
+* Above 600 pins begins to reduce production yields as well as increase
+ the cost of testing and packaging.
+
+We can look at larger higher-power ASICs either later or, if funding
+is made available, immediately.
+
+Recent applications to NLNet (Oct 2019) are for a test chip in 180nm,
+64 bit, single core dual issue, around 300 to 350mhz. This will provide
+the confidence to go to higher geometries, as well as be a commercially
+viable embedded product in its own right.
+
+# Business Objectives
-We seek investors, sponsors, engineers and potential customers, who are
-interested in the creation and use of an entirely libre low-power mobile
-class system-on-a-chip. Comparative benchmark performance, pincount and
-price is the Allwinner A64, except that the power budget target is 2.5 watts
-in a 16x16mm 320 to 360 pin 0.8mm FBGA package.
+See [[3d_gpu/business_objectives]]
-See:
+# Links:
-* [[libre_3d_gpu]]
+* [[shakti/m_class/libre_3d_gpu]]
* [[discussion]]
-*
-*
+* [[resources]]
+* [[overview]]
+* [[3d_gpu/funding]]
+* [[3d_gpu/architecture]]
+* Founding [[charter]]
+* Mailing list
+* Crowdsupply page
+* Wiki
+* Git repositories
+* Bugtracker
+* Kazan Vulkan Driver (including 3D engine)
+* [NLNet 2019 Milestones](http://bugs.libre-riscv.org/buglist.cgi?columnlist=assigned_to%2Cbug_status%2Cresolution%2Cshort_desc%2Ccf_budget&f1=cf_nlnet_milestone&o1=equals&query_format=advanced&resolution=---&v1=NLnet.2019.02)
+* NLNet Project Page
+* [[nlnet_proposals]]
+* [[llvm]]
-Progress:
+# Progress:
+* Jan 2020: New team members, Yehowshua and Michael. Last-minute attendance of FOSDEM2020
+* Dec 2019: Second round NLNet questions answered. External Review completed. 6 NLNet proposals accepted (EUR 200,000+)
+* Nov 2019: Alternative FP library to Berkeley softfloat developed. NLNet first round questions answered.
+* Oct 2019: 3D Standards continued. POWER ISA considered. Open 3D Alliance begins. NLNet funding applications submitted.
+* Sep 2019: 3D Standards continued. Additional NLNet Funding proposals discussed.
+* Aug 2019: Development of "Transcendentals" (SIN/COS/ATAN2) Specifications
+* Jul 2019: Sponsorship from Purism received. IEEE754 FP Mul, Add, DIV,
+ FCLASS and FCVT pipelines completed.
+* Jun 2019: IEEE754 FP Mul, Add, and FSM "DIV" completed.
+* May 2019: 6600-style scoreboard started
+* Apr 2019: NLnet funding approved by independent review committee
+* Mar 2019: NLnet funding application first and second phase passed
+* Mar 2019: First successful nmigen pipeline milestone achieved with IEEE754 FADD
+* Feb 2019: Conversion of John Dawson's IEEE754 FPU to nmigen started
+* Jan 2019: Second version Simple-V preliminary proposal (suited to LLVM)
* 2017 - Nov 2018: Simple-V specification preliminary draft completed
* Aug 2018 - Nov 2018: spike-sv implementation of draft spec completed
* Aug 2018: Kazan Vulkan Driver initiated
@@ -29,6 +86,7 @@ Progress:
# News Articles
+*
*
*
*
@@ -41,3 +99,57 @@ Progress:
*
*
*
+*
+*
+*
+*
+*
+*
+*
+*
+*
+*
+* Dec 2019 ProLinux
+* Dec 2019 Phoronix
+
+# Information Resources and Tutorials
+
+*
+*
+*
+*
+*
+*
+*
+*
+*
+*
+* -
+*
+*
+*
+*
+*
+*
+*
+*
+*
+*
+*
+*
+*
+*
+*
+*
+* Fundamentals of Modern VLSI Devices
+
+# Analog Simulation
+
+*
+*
+*
+*
+
+# Evaluations
+
+* [[openpower]]