X-Git-Url: https://git.libre-soc.org/?a=blobdiff_plain;f=3d_gpu.mdwn;h=68b636bb71197fbdb6ff9664facc36507f9b7e7c;hb=d155294d4c16327b3d2c63b05e326cf9a60825b2;hp=7ef5e85a1edce60d445d4e84e6bbf6bfe3f5078c;hpb=3d518fdce982fd58c1b2fd68de8e6094458ced79;p=libreriscv.git
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# RISC-V 3D GPU / CPU / VPU
+Creating a trustworthy processor for the world.
+
Note: this is a **hybrid** CPU, VPU and GPU. It is not, as many news articles
-are implying, a "dedicated exclusive GPU". The option exists to **create**
-a stand-alone GPU product. It is being *designed* to be a **complete**
-all-in-one processor (System-on-a-Chip).
+are implying, a "dedicated exclusive GPU". The option exists to *create*
+a stand-alone GPU product (contact us if this is a product that you want).
+Our primary goal is to design a **complete** all-in-one processor
+(System-on-a-Chip) that happens to include libre-licensed VPU and GPU
+accelerated instructions as part of the actual - main - CPU itself.
+
+We seek investors, sponsors (whose contributions thanks to NLNet may be
+tax-deductible), engineers and potential customers, who are
+interested, as a first product, in the creation and use of an entirely
+libre low-power mobile class system-on-a-chip. Comparative benchmark
+performance, pincount and price is the Allwinner A64, except that the
+power budget target is 2.5 watts in a 16x16mm 320 to 360 pin 0.8mm
+FBGA package. Instead of single-issue higher clock rate, the design is
+multi-issue, aiming for around 800mhz.
+
+The lower pincount, lower power, and higher BGA pitch is all to reduce
+the cost of product development when it comes to PCB design and layout:
+
+* Above 4 watts requires metal packages, greater attention to thermal
+ management in the PCB design and layout, and much pricier PMICs.
+* 0.6mm pitch BGA and below requires much more expensive PCB manufacturing
+ equipment and more costly PCBA techniques.
+* Above 600 pins begins to reduce production yields as well as increase
+ the cost of testing and packaging.
+
+We can look at larger higher-power ASICs either later or, if funding
+is made available, immediately.
+
+Recent applications to NLNet (Oct 2019) are for a test chip in 180nm,
+64 bit, single core dual issue, around 300 to 350mhz. This will provide
+the confidence to go to higher geometries, as well as be a commercially
+viable embedded product in its own right.
-We seek investors, sponsors, engineers and potential customers, who are
-interested in the creation and use of an entirely libre low-power mobile
-class system-on-a-chip. Comparative benchmark performance, pincount and
-price is the Allwinner A64, except that the power budget target is 2.5 watts
-in a 16x16mm 320 to 360 pin 0.8mm FBGA package.
+# Business Objectives
-See:
+See [[3d_gpu/business_objectives]]
+
+* the project shall be a hybrid CPU-GPU-VPU
+* the project shall be commercial and mass-volume (100 million units
+ and above)
+* the project shall be entirely transparent so that end-users will be
+ able to trust it
+* the source code shall be available at all times for all components
+ for BUSINESS reasons, making development and use of SDKs dead simple
+ and aiding and assisting developers AND BUSINESSES in debugging and thus
+ hugely saving them money.
+
+Reasoning:
+
+* If the processor is not a hybrid CPU-GPU-VPU, the
+ complexity involved in developing a split shared-memory CPU-GPU both
+ at a hardware and a software level will be so costly it will jeapordise
+ the project.
+* The project is commercial and mass-volume because there are plenty
+ of academic designs (none of them reaching production where people
+ may benefit), and "Open" designs, created by the Open Hardware
+ Community, sadly due to the high cost of producing ASICs, tend to be
+ focussed on markets that would have been great about twenty to thirty
+ years ago.
+* Transparency is a key business objective. It is a Unique Selling Point
+ that the processor is developed in a fashion that, should it be
+ independently audited, no opportunity for spying back-door co-processors
+ will be found to have "made their way surreptitiously - or overtly -
+ into the design". Yes, GCHQ: I know about the conversation you had
+ with nCipher (and, to their everlasting credit, that they told you
+ to take a hike)
+
+# Links:
* [[shakti/m_class/libre_3d_gpu]]
* [[discussion]]
+* [[resources]]
+* [[overview]]
+* [[3d_gpu/funding]]
+* [[3d_gpu/architecture]]
* Founding [[charter]]
* Mailing list
* Crowdsupply page
@@ -23,9 +86,21 @@ See:
* Bugtracker
* Kazan Vulkan Driver (including 3D engine)
* [NLNet 2019 Milestones](http://bugs.libre-riscv.org/buglist.cgi?columnlist=assigned_to%2Cbug_status%2Cresolution%2Cshort_desc%2Ccf_budget&f1=cf_nlnet_milestone&o1=equals&query_format=advanced&resolution=---&v1=NLnet.2019.02)
+* NLNet Project Page
+* [[nlnet_proposals]]
+* [[llvm]]
-Progress:
+# Progress:
+* Dec 2019: Second round NLNet questions answered. External Review completed. 6 NLNet proposals accepted (EUR 200,000+)
+* Nov 2019: Alternative FP library to Berkeley softfloat developed. NLNet first round questions answered.
+* Oct 2019: 3D Standards continued. POWER ISA considered. Open 3D Alliance begins. NLNet funding applications submitted.
+* Sep 2019: 3D Standards continued. Additional NLNet Funding proposals discussed.
+* Aug 2019: Development of "Transcendentals" (SIN/COS/ATAN2) Specifications
+* Jul 2019: Sponsorship from Purism received. IEEE754 FP Mul, Add, DIV,
+ FCLASS and FCVT pipelines completed.
+* Jun 2019: IEEE754 FP Mul, Add, and FSM "DIV" completed.
+* May 2019: 6600-style scoreboard started
* Apr 2019: NLnet funding approved by independent review committee
* Mar 2019: NLnet funding application first and second phase passed
* Mar 2019: First successful nmigen pipeline milestone achieved with IEEE754 FADD
@@ -40,6 +115,7 @@ Progress:
# News Articles
+*
*
*
*
@@ -54,6 +130,15 @@ Progress:
*
*
*
+*
+*
+*
+*
+*
+*
+*
+*
+*
# Information Resources and Tutorials
@@ -81,6 +166,10 @@ Progress:
*
*
*
+*
+*
+*
+* Fundamentals of Modern VLSI Devices
# Analog Simulation
@@ -88,3 +177,7 @@ Progress:
*
*
*
+
+# Evaluations
+
+*[[openpower]]