X-Git-Url: https://git.libre-soc.org/?a=blobdiff_plain;f=3d_gpu.mdwn;h=89a432b62622cb3bddcf6bb14547eed9dd7ed0ef;hb=8887102b43cee76dfab68ff78707d23e403d04f6;hp=d16a58c54f15cdb4fd81ae22c869754b28de02dc;hpb=4a4952ecc1ab6c626e8aa97b275b32e0d23b4781;p=libreriscv.git diff --git a/3d_gpu.mdwn b/3d_gpu.mdwn index d16a58c54..89a432b62 100644 --- a/3d_gpu.mdwn +++ b/3d_gpu.mdwn @@ -27,6 +27,8 @@ the cost of product development when it comes to PCB design and layout: We can look at larger higher-power ASICs either later or, if funding is made available, immediately. +Recent applications to NLNet (Oct 2019) are for a test chip in 180nm, 64 bit, single core dual issue, around 300 to 350mhz. This will provide the confidence to go to higher geometries, as well as be a commercially viable embedded product in its own right. + See: * [[shakti/m_class/libre_3d_gpu]] @@ -45,6 +47,11 @@ See: Progress: +* Dec 2019: Second round NLNet questions answered. External Review completed. 6 NLNet proposals accepted (EUR 200,000+) +* Nov 2019: Alternative FP library to Berkeley softfloat developed. NLNet first round questions answered. +* Oct 2019: 3D Standards continued. POWER ISA considered. Open 3D Alliance begins. NLNet funding applications submitted. +* Sep 2019: 3D Standards continued. Additional NLNet Funding proposals discussed. +* Aug 2019: Development of "Transcendentals" (SIN/COS/ATAN2) Specifications * Jul 2019: Sponsorship from Purism received. IEEE754 FP Mul, Add, DIV, FCLASS and FCVT pipelines completed. * Jun 2019: IEEE754 FP Mul, Add, and FSM "DIV" completed. @@ -63,6 +70,7 @@ Progress: # News Articles +* * * * @@ -123,3 +131,7 @@ Progress: * * * + +# Evaluations + +*[[openpower]]