X-Git-Url: https://git.libre-soc.org/?a=blobdiff_plain;f=3d_gpu.mdwn;h=8b37737fd7bf2c08ecf209524d9cc6fa5d8dc9e9;hb=acd4b52a605a657c986f4a14b83bab0e1019b3c2;hp=1702733ebe0412554d57908fd9a7bcc43198b396;hpb=759cc75beb2c8bc44c6fc98e05acaf4291e3b42a;p=libreriscv.git diff --git a/3d_gpu.mdwn b/3d_gpu.mdwn index 1702733eb..8b37737fd 100644 --- a/3d_gpu.mdwn +++ b/3d_gpu.mdwn @@ -1,29 +1,138 @@ -# RISC-V 3D GPU / CPU / VPU +See architectural details [here](./architecture) + +# "Gaddie Pitch" (1) for LibreSOC + +| What we do | Benefits | Feelings | +| ------------------------ | --------------------- | ----------------------- | +| design high-performance | No spying backdoors, | Much less frustrated | +| efficient and simpler | greatly reduced time | when developing products| +| processors with built-in | and cost to market | using e.g. China-based | +| 3D and Video capability | Simpler debugging | products. End-customer | +| in a fully-transparent | Full transparency | stops complaining, | +| fashion. | for their customers | Risk and worry gone. | + +## You know how... + +You know how for computers, you really have no idea how they work? And +how you keep having to replace them with upgrades? Turns out that +it's very difficult for medium-sized businesses to design lower-cost products +because the only cheap processors (almost always from China) do not respect +Copyright law, provide almost zero documentation, and even Intel processors +are known to have spying backdoor co-processors in them? + +## Well what we do is... + +Well, what we do is: design 3D-capable efficient processors based on +full transparency. All source code, right to the bedrock, hardware +and software. We don't tell customers "trust us", we say "go have a +specialist audit the full source, independently". If there's ever +some documentation missing, the customer can check for themselves when +designing *their* product around ours. + +## In fact... + +In fact, one customer that we're talking to is so fed up with a Chinese-based +$35 component that they are using in a $3000 product, where they are having +to spend considerable resources to *reverse-engineer* the China component, +they are so fed up that they're willing to bet on our product even before we've +completed it, they believe in the approach and our design that much. + +# "Gaddie Pitch" (1.5) for LibreSOC + EOMA68 + +## What we do + +Design modular computing appliances based around "Computer Card" standards +where the "Computer Card" may be upgraded, swapped, shared, re-programmed, +re-purposed, and re-used. + +## Benefits + +Almost too numerous to describe. Not just the right to repair: the right +to redesign and many more. "Computer Card" has the data *and* the apps on +it, so goodbye file incompatibility: just move **the whole computer** from a +TV slot to a Laptop slot to a Tablet slot to a Desktop slot. Also the cost +savings and environmental savings are enormous. Keep the same $300 Laptop +"Housing" for 15 years, upgrade its parts over time, and not only buy a +new Computer Card for $30 every 2 years, keep the old one as a "spare", +give it to the kids, re-program it for watching Videos, the list is endless. + +## Feelings + +Every person we've spoken to, once they get around the confusion of the +idea of a "Computer" being inside a "Card" rather than "part of A Laptop", +has loved both the environmental as well as the cost savings. + +# "Gaddie Pitch" (2) for LibreSOC + +Cole TODO + +# Hybrid 3D GPU / CPU / VPU + +Creating a trustworthy processor for the world. + +Our [[3d_gpu/business_objectives]] Note: this is a **hybrid** CPU, VPU and GPU. It is not, as many news articles -are implying, a "dedicated exclusive GPU". The option exists to **create** -a stand-alone GPU product. It is being *designed* to be a **complete** -all-in-one processor (System-on-a-Chip). +are implying, a "dedicated exclusive GPU". The option exists to *create* +a stand-alone GPU product (contact us if this is a product that you want). +Our primary goal is to design a **complete** all-in-one processor +(System-on-a-Chip) that happens to include libre-licensed VPU and GPU +accelerated instructions as part of the actual - main - CPU itself. This greatly simplifies driver development, applications integration and debugging, reducing costs and time to market in the process. + +We seek investors, sponsors (whose contributions thanks to NLNet may be +tax-deductible), engineers and potential customers, who are +interested, as a first product, in the creation and use of an entirely +libre low-power mobile class system-on-a-chip +[[shakti/m_class/]]. Comparative benchmark +performance, pincount and price is the Allwinner A64, except that the +power budget target is 2.5 watts in a 16x16mm 320 to 360 pin 0.8mm +FBGA package. Instead of single-issue higher clock rate, the design is +multi-issue, aiming for around 800mhz. -We seek investors, sponsors, engineers and potential customers, who are -interested in the creation and use of an entirely libre low-power mobile -class system-on-a-chip. Comparative benchmark performance, pincount and -price is the Allwinner A64, except that the power budget target is 2.5 watts -in a 16x16mm 320 to 360 pin 0.8mm FBGA package. +The lower pincount, lower power, and higher BGA pitch is all to reduce +the cost of product development when it comes to PCB design and layout: -See: +* Above 4 watts requires metal packages, greater attention to thermal + management in the PCB design and layout, and much pricier PMICs. +* 0.6mm pitch BGA and below requires much more expensive PCB manufacturing + equipment and more costly PCBA techniques. +* Above 600 pins begins to reduce production yields as well as increase + the cost of testing and packaging. -* [[shakti/m_class/libre_3d_gpu]] -* [[discussion]] -* Mailing list -* Crowdsupply page -* Wiki -* Git repositories -* Bugtracker -* Kazan Vulkan Driver (including 3D engine) +We can look at larger higher-power ASICs either later or, if funding +is made available, immediately. -Progress: +Recent applications to NLNet (Oct 2019) are for a test chip in 180nm, +64 bit, single core dual issue, around 300 to 350mhz. This will provide +the confidence to go to higher geometries, as well as be a commercially +viable embedded product in its own right. Tapeout deadline is Oct 2020. +See [[3d_gpu/articles]] online. + +# Progress: + +* Oct 2020 [[180nm_Oct2020/ls180/]] pinouts decided, code-freeze initiated + for 180nm test ASIC, GDSII deadline set of Dec 2nd. +* Sep 2020: [first boot](https://youtu.be/72QmWro9BSE) of Litex BIOS on a Versa ECP5 at 55mhz. DDR3 RAM initialisation successful. 180nm ASIC pinouts started [[180nm_Oct2020/ls180]] +* Aug 2020: [first boot](https://libre-soc.org/3d_gpu/libresoc_litex_bios_first_execution_2020-08-06_16-15.png) of litex BIOS in verilator simulation +* Jul 2020: first ppc64le "hello world" binary executed. 80,000 gate coriolis2 auto-layout completed with 99.98% routing. Wishbone MoU signed making available access to an additional EUR 50,000 donations from NLNet. XDC2020 and OpenPOWER conference submissions entered. +* Jun 2020: core unit tests and pipeline formal correctness proofs in place. +* May 2020: first integer pipelines (ALU, Logical, Branch, Trap, SPR, ShiftRot, Mul, Div) and register files (XER, CR, INT, FAST, SPR) started. +* Mar 2020: Coriolis2 Layout experiments successful. 6600 Memory Architecture + exploration started. OpenPOWER ISA decoder started. Two new people: + Alain and Jock. +* Feb 2020: OpenPower Foundation EULA released. Coriolis2 Layout experimentation begun. Dynamic Partitioned SIMD ALU created. +* Jan 2020: New team members, Yehowshua and Michael. Last-minute attendance of FOSDEM2020 +* Dec 2019: Second round NLNet questions answered. External Review completed. 6 NLNet proposals accepted (EUR 200,000+) +* Nov 2019: Alternative FP library to Berkeley softfloat developed. NLNet first round questions answered. +* Oct 2019: 3D Standards continued. POWER ISA considered. Open 3D Alliance begins. NLNet funding applications submitted. +* Sep 2019: 3D Standards continued. Additional NLNet Funding proposals discussed. +* Aug 2019: Development of "Transcendentals" (SIN/COS/ATAN2) Specifications +* Jul 2019: Sponsorship from Purism received. IEEE754 FP Mul, Add, DIV, + FCLASS and FCVT pipelines completed. +* Jun 2019: IEEE754 FP Mul, Add, and FSM "DIV" completed. +* May 2019: 6600-style scoreboard started +* Apr 2019: NLnet funding approved by independent review committee * Mar 2019: NLnet funding application first and second phase passed * Mar 2019: First successful nmigen pipeline milestone achieved with IEEE754 FADD * Feb 2019: Conversion of John Dawson's IEEE754 FPU to nmigen started @@ -35,34 +144,12 @@ Progress: * Sep 2018: Crowdsupply pre-launch page up (for updates) * Dec 2018: preliminary floorplan and architecture designed (comp.arch) -# News Articles - -* -* -* -* -* -* -* -* -* -* -* -* -* -* - -# Information Resources and Tutorials - -* -* -* -* -* -* -* -* -* -* -* - -* + +# Evaluations + +* [[openpower]] + +# Drivers + +* [[3d_gpu/opencl]] +* [[3d_gpu/mesa]]