X-Git-Url: https://git.libre-soc.org/?a=blobdiff_plain;f=3d_gpu.mdwn;h=f455c8381b57db7bdcc3472ae1c801a0bff33852;hb=7e6cb373140c41b8797287fa933fed68b2afb9fe;hp=7ae5a379965f30a794711878f825b8773ba34797;hpb=3957a7d90f924a9af491ffbd9db1c4469500fec5;p=libreriscv.git

diff --git a/3d_gpu.mdwn b/3d_gpu.mdwn
index 7ae5a3799..f455c8381 100644
--- a/3d_gpu.mdwn
+++ b/3d_gpu.mdwn
@@ -2,19 +2,38 @@
 
 Note: this is a **hybrid** CPU, VPU and GPU.  It is not, as many news articles
 are implying, a "dedicated exclusive GPU".  The option exists to **create**
-a stand-alone GPU product.  It is being *designed* to be a **complete**
-all-in-one processor (System-on-a-Chip).
+a stand-alone GPU product (contact us if this is a product that you want).
+Our primary goal is to design a **complete** all-in-one processor
+(System-on-a-Chip) that happens to include a libre-licensed VPU and GPU.
 
 We seek investors, sponsors, engineers and potential customers, who are
-interested in the creation and use of an entirely libre low-power mobile
-class system-on-a-chip.  Comparative benchmark performance, pincount and
-price is the Allwinner A64, except that the power budget target is 2.5 watts
-in a 16x16mm 320 to 360 pin 0.8mm FBGA package.
+interested, as a first product, in the creation and use of an entirely
+libre low-power mobile class system-on-a-chip.  Comparative benchmark
+performance, pincount and price is the Allwinner A64, except that the
+power budget target is 2.5 watts in a 16x16mm 320 to 360 pin 0.8mm
+FBGA package.  Instead of single-issue higher clock rate, the design is
+multi-issue, aiming for around 800mhz.
+
+The lower pincount, lower power, and higher BGA pitch is all to reduce
+the cost of product development when it comes to PCB design and layout:
+
+* Above 4 watts requires metal packages, greater attention to thermal
+  management in the PCB design and layout, and much pricier PMICs.
+* 0.6mm pitch BGA and below requires much more expensive PCB manufacturing
+  equipment and more costly PCBA techniques.
+* Above 600 pins begins to reduce production yields as well as increase
+  the cost of testing and packaging.
+
+We can look at larger higher-power ASICs either later or, if funding
+is made available, immediately.
+
+Recent applications to NLNet (Oct 2019) are for a test chip in 180nm, 64 bit, single core dual issue, around 300 to 350mhz.  This will provide the confidence to go to higher geometries, as well as be a commercially viable embedded product in its own right.
 
 See:
 
 * [[shakti/m_class/libre_3d_gpu]]
 * [[discussion]]
+* [[resources]]
 * Founding [[charter]]
 * Mailing list <http://lists.libre-riscv.org/pipermail/libre-riscv-dev/>
 * Crowdsupply page <https://www.crowdsupply.com/libre-risc-v/m-class>
@@ -23,9 +42,20 @@ See:
 * Bugtracker <http://bugs.libre-riscv.org>
 * Kazan Vulkan Driver (including 3D engine) <https://salsa.debian.org/Kazan-team/kazan>
 * [NLNet 2019 Milestones](http://bugs.libre-riscv.org/buglist.cgi?columnlist=assigned_to%2Cbug_status%2Cresolution%2Cshort_desc%2Ccf_budget&f1=cf_nlnet_milestone&o1=equals&query_format=advanced&resolution=---&v1=NLnet.2019.02)
+* NLNet Project Page <https://nlnet.nl/project/Libre-RISCV/>
+* [[nlnet_proposals]]
 
 Progress:
 
+* Dec 2019: Second round NLNet questions answered.
+* Nov 2019: Alternative FP library to Berkeley softfloat developed. NLNet first round questions answered.
+* Oct 2019: 3D Standards continued.  POWER ISA considered.  Open 3D Alliance begins.  NLNet funding applications submitted.
+* Sep 2019: 3D Standards continued.  Additional NLNet Funding proposals discussed.
+* Aug 2019: Development of "Transcendentals" (SIN/COS/ATAN2) Specifications
+* Jul 2019: Sponsorship from Purism received.  IEEE754 FP Mul, Add, DIV,
+  FCLASS and FCVT pipelines completed.
+* Jun 2019: IEEE754 FP Mul, Add, and FSM "DIV" completed.
+* May 2019: 6600-style scoreboard started
 * Apr 2019: NLnet funding approved by independent review committee
 * Mar 2019: NLnet funding application first and second phase passed
 * Mar 2019: First successful nmigen pipeline milestone achieved with IEEE754 FADD
@@ -40,6 +70,7 @@ Progress:
 
 # News Articles
 
+* <https://www.phoronix.com/forums/forum/hardware/processors-memory/1133806-libre-risc-v-open-source-effort-now-looking-at-power-instead-of-risc-v/page7>
 * <https://hub.packtpub.com/a-libre-gpu-effort-based-on-risc-v-rust-llvm-and-vulkan-by-the-developer-of-an-earth-friendly-computer/>
 * <https://riscv.org/2018/10/packt-hub-article-a-libre-gpu-effort-based-on-risc-v-rust-llvm-and-vulkan-by-the-developer-of-an-earth-friendly-computer/>
 * <https://www.reddit.com/r/RISCV/comments/9jts9t/theres_a_new_libre_gpu_effort_building_on_riscv/>
@@ -54,6 +85,14 @@ Progress:
 * <https://www.reddit.com/domain/libre-riscv.org/>
 * <https://hardware.slashdot.org/comments.pl?sid=13447940&cid=58160868>
 * <https://www.phoronix.com/forums/forum/hardware/graphics-cards/1080755-libre-risc-v-gpu-aiming-for-2-5-watt-power-draw-continues-being-plotted/page5>
+* <https://www.phoronix.com/forums/forum/hardware/processors-memory/1070828-more-details-on-the-proposed-simple-v-extension-to-risc-v-for-gpu-workloads>
+* <https://slashdot.org/submission/9750302/nlnet-funds-development-of-a-libre-risc-v-3d-cpu>
+* <https://hardware.slashdot.org/story/19/06/02/0153243/nlnet-funds-development-of-a-libre-risc-v-3d-cpu>
+* <https://www.phoronix.com/forums/forum/hardware/graphics-cards/1104124-libre-risc-v-snags-50k-eur-grant-to-work-on-its-risc-v-3d-gpu-chip/page6>
+* <https://news.ycombinator.com/item?id=21112341>
+* <https://www.reddit.com/r/RISCV/comments/db04j3/libreriscv_3d_cpugpu_seeks_grants_for_ambitious/>
+* <https://hardware.slashdot.org/story/19/09/29/1845252/libre-risc-v-3d-cpugpu-seeks-grants-for-ambitious-expansion>
+* <https://forums.puri.sm/t/risc-v-m-class-effort-and-purism-donation/6528/15>
 
 # Information Resources and Tutorials
 
@@ -80,6 +119,11 @@ Progress:
 * <http://smallcultfollowing.com/babysteps/blog/2019/04/19/aic-adventures-in-consensus/>
 * <http://www.crnhq.org/12-Skills-Summary.aspx?rw=c>
 * <http://bugs.libre-riscv.org/buglist.cgi?columnlist=assigned_to%2Cbug_status%2Cresolution%2Cshort_desc%2Ccf_budget&f1=cf_nlnet_milestone&o1=equals&query_format=advanced&resolution=---&v1=NLnet.2019.02>
+* <https://pdfs.semanticscholar.org/5060/4e9aff0e37089c4ab9a376c3f35761ffe28b.pdf>
+* <http://www.acsel-lab.com/arithmetic/arith15/papers/ARITH15_Takagi.pdf>
+* <https://youtu.be/o5Ihqg72T3c>
+* <http://flopoco.gforge.inria.fr/>
+* Fundamentals of Modern VLSI Devices <https://groups.google.com/a/groups.riscv.org/d/msg/hw-dev/b4pPvlzBzu0/7hDfxArEAgAJ>
 
 # Analog Simulation
 
@@ -87,3 +131,7 @@ Progress:
 * <http://www.vlsiacademy.org/open-source-cad-tools.html>
 * <http://ngspice.sourceforge.net/adms.html>
 * <https://en.wikipedia.org/wiki/Verilog-AMS#Open_Source_Implementations>
+
+# Evaluations
+
+*[[openpower]]