X-Git-Url: https://git.libre-soc.org/?a=blobdiff_plain;f=45nm_Fall2022.mdwn;h=a73ed396e80e9c17dec382a624d1c7ff19287777;hb=b1331f37e6b41ac133f4286486a4af27b3f7fc1a;hp=87f0ded89a563516b3e20d2086cd777a7f16bd10;hpb=91bb73687a48bf71486d19768b6449626a8dc41d;p=libreriscv.git

diff --git a/45nm_Fall2022.mdwn b/45nm_Fall2022.mdwn
index 87f0ded89..a73ed396e 100644
--- a/45nm_Fall2022.mdwn
+++ b/45nm_Fall2022.mdwn
@@ -1,26 +1,39 @@
-# Specs
+# Specs for 2022 SOC
+
+## Applications
+
+ - We are providing open source drivers for the GPU,
+hopefully completed by Fall 2022.
+ - Given that POWER CPUs do not have GPUs, RaptorCS
+would like the LibreSOC to be able function as a
+discrete GPU in PCIE slave mode for POWER9 CPUs.
+ - Lastly, RaptorCS would like to manufacture single
+board computers.
 
 ## Devices
  - 4 Core POWER CPU
- - SimpleV GPU
- - BMC
+ - SimpleV Capability and GPU Instructions
  - IOMMU
  - Coherent Accelerator Processor Proxy (CAPP) functional unit
+ - PCIe host Controller
+ - PCIe Slave controller(RaptorCS wants to use LibreSOC as a GPU on their POWER mobos)
+ - BMC - enables LibreSOC to become a discrete GPU with video output and ethernet.
+ - RGB/TTL framebuffer VGA/LCD PHY from Richard Herveille, RoaLogic.
 
 ## Interfaces
 
 ### Advanced
 
  - SERDES - 10rx, 14tx
-   - 4tx, 4rx for [OMI(DDR4](https://openpowerfoundation.org/wp-content/uploads/2018/10/Jeff-Steuchli.OpenCAPI-OPS-OMI.pdf) on top of SERDES with OpenCAPI protocol) @25GHz
+   - 4tx, 4rx for [OMI(DDR4](https://openpowerfoundation.org/wp-content/uploads/2018/10/Jeff-Steuchli.OpenCAPI-OPS-OMI.pdf) on top of SERDES with OpenCAPI protocol) @5GHz
    - 2tx, 2rx for ethernet
-   - 4tx, 4rx for PCIE and other CAPI devices
-   - 3tx for HDMI
+   - 4tx, 4rx for PCIe and other CAPI devices
+   - 3tx for HDMI (note: requires HDMI Trademark Licensing and Compliance Testing)
  - [OpenFSI](https://openpowerfoundation.org/?resource_lib=field-replaceable-unit-fru-service-interface-fsi-openfsi-specification) instead of JTAG
    - [Raptor HDL](https://gitlab.raptorengineering.com/raptor-engineering-public/lpc-spi-bridge-fpga)
    - [Raptor Libsigrok](https://gitlab.raptorengineering.com/raptor-engineering-public/dsview/-/tree/master/libsigrokdecode4DSL/decoders/fsi)
- - USB - [Luna USB](https://github.com/greatscottgadgets/luna)
-with [USB3300 PHY](https://www.microchip.com/wwwproducts/en/USB3300#datasheet-toggle)
+ - USB 2.0 - [Luna USB](https://github.com/greatscottgadgets/luna)
+with [USB3300 PHY](https://www.microchip.com/wwwproducts/en/USB3300#datasheet-toggle) (Tested max at 333MB/s with Luna on ECP5)
 
 ### Basic
 
@@ -33,10 +46,11 @@ These should be easily doable with LiteX.
 * [[shakti/m_class/QSPI]]
 * [[shakti/m_class/LPC]]
 * [[shakti/m_class/EINT]]
+* [[shakti/m_class/RGBTTL]] in conjunction with TI TFP410a or Chrontel converter
 
 ## Protocols
  - IPMT over i2c to talk to the BMC
    - [Intel Spec Sheet](https://www.intel.com/content/dam/www/public/us/en/documents/product-briefs/second-gen-interface-spec-v2.pdf)
    - [RaptorCS HDL](https://gitlab.raptorengineering.com/raptor-engineering-public/lpc-spi-bridge-fpga/blob/master/ipmi_bt_slave.v)
- - Bootloader over LPC to Flexver
+ - Reset Vector is set Flexver address over LPC
    - [Whitepaper](https://www.raptorengineering.com/TALOS/documentation/flexver_intro.pdf)