X-Git-Url: https://git.libre-soc.org/?a=blobdiff_plain;f=A_Harmonised_RVV_and_Packed_SIMD.mdwn;h=452c4cf1c323c34cf7bdfcb6cd5ba9c6f09531d1;hb=f4e206cc481e8a6d1c507b8a31e9e236d3f3cf7a;hp=8c3bc9fede7ba97302edb9fa2b93dc6bae9ccfc9;hpb=70f76e05ce461156f5456d4b0b70a9bd8fd3d885;p=libreriscv.git

diff --git a/A_Harmonised_RVV_and_Packed_SIMD.mdwn b/A_Harmonised_RVV_and_Packed_SIMD.mdwn
index 8c3bc9fed..452c4cf1c 100644
--- a/A_Harmonised_RVV_and_Packed_SIMD.mdwn
+++ b/A_Harmonised_RVV_and_Packed_SIMD.mdwn
@@ -90,7 +90,7 @@ The above are pure subsets of valid RVV VCFG configurations (and hence forward c
 
 ## 16-bit Shifts
 
-SRA[I]16/SRL[I]16/SLL[I]16 to be mapped to VOP shift instructions in same manner as ADD16/SUB16  ie: map to signed r16-23 and unsigned r24-29 register banks in default vdcfg CSR setting
+SRA[I]16/SRL[I]16/SLL[I]16 to be mapped to VOP shift instructions in same manner as ADD16/SUB16
 
 The “K” (Saturation) and “u” (Rounding) variants could be encoded using VOP’s mm field (mm=01 is saturated or rounded shift, mm=00 is standard VOP shift)
 
@@ -101,7 +101,13 @@ The “K” (Saturation) and “u” (Rounding) variants could be encoded using
 | SRA16.u rt, ra, rb   | Rounding Shift right arithmetic     | VSRA (r16 <= rt,ra,rb <= r29), mm=01|
 | SRAI16.u rt, ra, im  | Rounding Shift right arithmetic imm | VSRAI (r16 <= rt,ra <= r29), mm=01|
 | SRL16 rt, ra, rb     | Shift right logical        | VSRL (r16 <= rt,ra,rb <= r29), mm=00|
-| SRLI16 rt, ra, im    | Shift right lgoical imm    | VSRLI (r16 <= rt,ra <= r29), mm=00|
+| SRLI16 rt, ra, im    | Shift right logical imm    | VSRLI (r16 <= rt,ra <= r29), mm=00|
 | SRL16.u rt, ra, rb   | Rounding Shift right logical     | VSRL (r16 <= rt,ra,rb <= r29), mm=01|
 | SRLI16.u rt, ra, im  | Rounding Shift right logical imm | VSLRI (r16 <= rt,ra <= r29), mm=01|
+| SLL16 rt, ra, rb     | Shift left logical         | VSLL (r16 <= rt,ra,rb <= r29), mm=00|
+| SLLI16 rt, ra, im    | Shift left logical imm     | VSLLI (r16 <= rt,ra <= r29), mm=00|
+| KSLL16 rt, ra, rb    | Saturating Shift left logical       | VSLL (r16 <= rt,ra,rb <= r29), mm=01|
+| KSLLI16 rt, ra, im   | Saturating Shift left logical imm   | VSLLI (r16 <= rt,ra <= r29), mm=01|
+| KSLRA16 rt, ra, rb    | Saturating Shift left logical or Shift right arithmetic              ||
+| KSLRA16.u rt, ra, rb  | Saturating Shift left logical or Rounding Shift right arithmetic     ||