X-Git-Url: https://git.libre-soc.org/?a=blobdiff_plain;f=CHANGELOG;h=069efd6f5586dbad5aaa27cea91864c244877668;hb=a4522d628296ccaea5e26b6cec1756f01475ceb5;hp=9402f9bbb1ef60e271ad0d60d3f9e343b4ce820e;hpb=8c509a5659d540dc41f6cc19ee6989fc249f519d;p=yosys.git

diff --git a/CHANGELOG b/CHANGELOG
index 9402f9bbb..069efd6f5 100644
--- a/CHANGELOG
+++ b/CHANGELOG
@@ -2,22 +2,55 @@
 List of major changes and improvements between releases
 =======================================================
 
-Yosys 0.12 .. Yosys 0.12-dev
+Yosys 0.13 .. Yosys 0.14
 --------------------------
 
-Yosys 0.11 .. Yosys 0.12
+ * Various
+    - Added $bmux and $demux cells and related optimization patterns.
+
+ * New commands and options
+    - Added "bmuxmap" and "dmuxmap" passes 
+    - Added "-fst" option to "sim" pass for writing FST files
+    - Added "-r", "-scope", "-start", "-stop", "-at", "-sim", "-sim-gate",
+      "-sim-gold" options to "sim" pass for co-simulation
+
+ * Anlogic support
+    - Added support for BRAMs
+
+Yosys 0.12 .. Yosys 0.13
 --------------------------
 
  * Various
-    - Added iopadmap native support for negative-polarity output enable
-    - ABC update
+    - Use "read" command to parse HDL files from Yosys command-line
+    - Added "yosys -r <topmodule>" command line option
+    - write_verilog: dump zero width sigspecs correctly
 
  * SystemVerilog
-    - Support parameters using struct as a wiretype
     - Fixed regression preventing the use array querying functions in case
       expressions and case item expressions
     - Fixed static size casts inadvertently limiting the result width of binary
       operations
+    - Fixed static size casts ignoring expression signedness
+    - Fixed static size casts not extending unbased unsized literals
+    - Added automatic `nosync` inference for local variables in `always_comb`
+      procedures which are always assigned before they are used to avoid errant
+      latch inference
+
+ * New commands and options
+    - Added "clean_zerowidth" pass
+
+ * Verific support
+    - Add YOSYS to the implicitly defined verilog macros in verific
+
+Yosys 0.11 .. Yosys 0.12
+--------------------------
+
+ * Various
+    - Added iopadmap native support for negative-polarity output enable
+    - ABC update
+
+ * SystemVerilog
+    - Support parameters using struct as a wiretype
 
  * New commands and options
     - Added "-genlib" option to "abc" pass