X-Git-Url: https://git.libre-soc.org/?a=blobdiff_plain;f=CHANGELOG;h=21fb8a3f5415c528c4bdbcc0a57654d87125c34d;hb=12c692f6eda7367527fde2a8aad49447a73aa643;hp=c280f4f123a72d3c351f910274243b7ec11cfced;hpb=da5f83039527bf50af001671744f351988c3261a;p=yosys.git diff --git a/CHANGELOG b/CHANGELOG index c280f4f12..21fb8a3f5 100644 --- a/CHANGELOG +++ b/CHANGELOG @@ -3,6 +3,25 @@ List of major changes and improvements between releases ======================================================= +Yosys 0.9 .. Yosys 0.9-dev +-------------------------- + + * Various + - Added "write_xaiger" backend + - Added "abc9" pass for timing-aware techmapping (experimental, FPGA only, no FFs) + - Added "synth_xilinx -abc9" (experimental) + - Added "synth_ice40 -abc9" (experimental) + - Added "synth -abc9" (experimental) + - Added "script -scriptwire + - "synth_xilinx" to now infer wide multiplexers (-widemux to enable) + - Added automatic gzip decompression for frontends + - Added $_NMUX_ cell type + - Added automatic gzip compression (based on filename extension) for backends + - Improve attribute and parameter encoding in JSON to avoid ambiguities between + bit vectors and strings containing [01xz]* + - Added "ice40_wrapcarry" to encapsulate SB_LUT+SB_CARRY pairs for techmapping + - Removed "ice40_unlut" + Yosys 0.8 .. Yosys 0.8-dev -------------------------- @@ -23,11 +42,9 @@ Yosys 0.8 .. Yosys 0.8-dev - Added "muxcover -nopartial" - Added "muxpack" pass - Added "pmux2shiftx -norange" - - Added "write_xaiger" backend - - Added "abc9" pass for timing-aware techmapping (experimental, FPGA only, no FFs) - - Added "synth_xilinx -abc9" (experimental) - - Added "synth_ice40 -abc9" (experimental) - - Added "synth -abc9" (experimental) + - Added "synth_xilinx -nocarry" + - Added "synth_xilinx -nowidelut" + - Added "synth_ecp5 -nowidelut" - "synth_xilinx" to now infer hard shift registers (-nosrl to disable) - Fixed sign extension of unsized constants with 'bx and 'bz MSB