X-Git-Url: https://git.libre-soc.org/?a=blobdiff_plain;f=CHANGELOG;h=36b64e111e9ac8bc09b03ceb3de9d9aff6ee1eeb;hb=6934f4bdd53cb226d0c8631eff691d9a96aebbce;hp=77d7551bf23ade8f5432dc7c0f8849ce5fbca29d;hpb=ca125bf41b6de9251f6396fd06ba7a50c7eb48c0;p=yosys.git diff --git a/CHANGELOG b/CHANGELOG index 77d7551bf..36b64e111 100644 --- a/CHANGELOG +++ b/CHANGELOG @@ -1,9 +1,457 @@ -List of changes and major improvements between releases +List of major changes and improvements between releases ======================================================= -Yosys 0.2.0 .. Yoys 0.3.0 +Yosys 0.8 .. Yosys 0.8-dev +-------------------------- + + * Various + - Added $changed support to read_verilog + - Added "write_edif -attrprop" + - Added "ice40_unlut" pass + - Added "opt_lut" pass + - Added "synth_ice40 -relut" + - Added "synth_ice40 -noabc" + - Added "gate2lut.v" techmap rule + - Added "rename -src" + - Added "equiv_opt" pass + - "synth_xilinx" to now infer hard shift registers, using new "shregmap -tech xilinx" + + +Yosys 0.7 .. Yosys 0.8 +---------------------- + + * Various + - Many bugfixes and small improvements + - Strip debug symbols from installed binary + - Replace -ignore_redef with -[no]overwrite in front-ends + - Added write_verilog hex dump support, add -nohex option + - Added "write_verilog -decimal" + - Added "scc -set_attr" + - Added "verilog_defines" command + - Remeber defines from one read_verilog to next + - Added support for hierarchical defparam + - Added FIRRTL back-end + - Improved ABC default scripts + - Added "design -reset-vlog" + - Added "yosys -W regex", "yosys -w regex", and "yosys -e regex" + - Added Verilog $rtoi and $itor support + - Added "check -initdrv" + - Added "read_blif -wideports" + - Added support for systemVerilog "++" and "--" operators + - Added support for SystemVerilog unique, unique0, and priority case + - Added "write_edif" options for edif "flavors" + - Added support for resetall compiler directive + - Added simple C beck-end (bitwise combinatorical only atm) + - Added $_ANDNOT_ and $_ORNOT_ cell types + - Added cell library aliases to "abc -g" + - Added "setundef -anyseq" + - Added "chtype" command + - Added "design -import" + - Added "write_table" command + - Added "read_json" command + - Added "sim" command + - Added "extract_fa" and "extract_reduce" commands + - Added "extract_counter" command + - Added "opt_demorgan" command + - Added support for $size and $bits SystemVerilog functions + - Added "blackbox" command + - Added "ltp" command + - Added support for editline as replacement for readline + - Added warnings for driver-driver conflicts between FFs (and other cells) and constants + - Added "yosys -E" for creating Makefile dependencies files + - Added "synth -noshare" + - Added "memory_nordff" + - Added "setundef -undef -expose -anyconst" + - Added "expose -input" + - Added specify/specparam parser support (simply ignore them) + - Added "write_blif -inames -iattr" + - Added "hierarchy -simcheck" + - Added an option to statically link abc into yosys + - Added protobuf back-end + - Added BLIF parsing support for .conn and .cname + - Added read_verilog error checking for reg/wire/logic misuse + - Added "make coverage" and ENABLE_GCOV build option + + * Changes in Yosys APIs + - Added ConstEval defaultval feature + - Added {get,set}_src_attribute() methods on RTLIL::AttrObject + - Added SigSpec::is_fully_ones() and Const::is_fully_ones() + - Added log_file_warning() and log_file_error() functions + + * Formal Verification + - Added "write_aiger" + - Added "yosys-smtbmc --aig" + - Added "always " to .smtc format + - Added $cover cell type and support for cover properties + - Added $fair/$live cell type and support for liveness properties + - Added smtbmc support for memory vcd dumping + - Added "chformal" command + - Added "write_smt2 -stbv" and "write_smt2 -stdt" + - Fix equiv_simple, old behavior now available with "equiv_simple -short" + - Change to Yices2 as default SMT solver (it is GPL now) + - Added "yosys-smtbmc --presat" (now default in SymbiYosys) + - Added "yosys-smtbmc --smtc-init --smtc-top --noinit" + - Added a brand new "write_btor" command for BTOR2 + - Added clk2fflogic memory support and other improvements + - Added "async memory write" support to write_smt2 + - Simulate clock toggling in yosys-smtbmc VCD output + - Added $allseq/$allconst cells for EA-solving + - Make -nordff the default in "prep" + - Added (* gclk *) attribute + - Added "async2sync" pass for single-clock designs with async resets + + * Verific support + - Many improvements in Verific front-end + - Added proper handling of concurent SVA properties + - Map "const" and "rand const" to $anyseq/$anyconst + - Added "verific -import -flatten" and "verific -import -extnets" + - Added "verific -vlog-incdir -vlog-define -vlog-libdir" + - Remove PSL support (because PSL has been removed in upstream Verific) + - Improve integration with "hierarchy" command design elaboration + - Added YOSYS_NOVERIFIC for running non-verific test cases with verific bin + - Added simpilied "read" command that automatically uses verific if available + - Added "verific -set- .." + - Added "verific -work " + + * New back-ends + - Added initial Coolrunner-II support + - Added initial eASIC support + - Added initial ECP5 support + + * GreenPAK Support + - Added support for GP_DLATCH, GP_SPI, GP_DCMx, GP_COUNTx, etc. + + * iCE40 Support + - Add "synth_ice40 -vpr" + - Add "synth_ice40 -nodffe" + - Add "synth_ice40 -json" + - Add Support for UltraPlus cells + + * MAX10 and Cyclone IV Support + - Added initial version of metacommand "synth_intel". + - Improved write_verilog command to produce VQM netlist for Quartus Prime. + - Added support for MAX10 FPGA family synthesis. + - Added support for Cyclone IV family synthesis. + - Added example of implementation for DE2i-150 board. + - Added example of implementation for MAX10 development kit. + - Added LFSR example from Asic World. + - Added "dffinit -highlow" for mapping to Intel primitives + + +Yosys 0.6 .. Yosys 0.7 +---------------------- + + * Various + - Added "yosys -D" feature + - Added support for installed plugins in $(DATDIR)/plugins/ + - Renamed opt_const to opt_expr + - Renamed opt_share to opt_merge + - Added "prep -flatten" and "synth -flatten" + - Added "prep -auto-top" and "synth -auto-top" + - Using "mfs" and "lutpack" in ABC lut mapping + - Support for abstract modules in chparam + - Cleanup abstract modules at end of "hierarchy -top" + - Added tristate buffer support to iopadmap + - Added opt_expr support for div/mod by power-of-two + - Added "select -assert-min -assert-max " + - Added "attrmvcp" pass + - Added "attrmap" command + - Added "tee +INT -INT" + - Added "zinit" pass + - Added "setparam -type" + - Added "shregmap" pass + - Added "setundef -init" + - Added "nlutmap -assert" + - Added $sop cell type and "abc -sop -I -P " + - Added "dc2" to default ABC scripts + - Added "deminout" + - Added "insbuf" command + - Added "prep -nomem" + - Added "opt_rmdff -keepdc" + - Added "prep -nokeepdc" + - Added initial version of "synth_gowin" + - Added "fsm_expand -full" + - Added support for fsm_encoding="user" + - Many improvements in GreenPAK4 support + - Added black box modules for all Xilinx 7-series lib cells + - Added synth_ice40 support for latches via logic loops + - Fixed ice40_opt lut unmapping, added "ice40_opt -unlut" + + * Build System + - Added ABCEXTERNAL and ABCURL make variables + - Added BINDIR, LIBDIR, and DATDIR make variables + - Added PKG_CONFIG make variable + - Added SEED make variable (for "make test") + - Added YOSYS_VER_STR make variable + - Updated min GCC requirement to GCC 4.8 + - Updated required Bison version to Bison 3.x + + * Internal APIs + - Added ast.h to exported headers + - Added ScriptPass helper class for script-like passes + - Added CellEdgesDatabase API + + * Front-ends and Back-ends + - Added filename glob support to all front-ends + - Added avail (black-box) module params to ilang format + - Added $display %m support + - Added support for $stop Verilog system task + - Added support for SystemVerilog packages + - Fixed procedural assignments to non-unique lvalues, e.g. {y,y} = {a,b} + - Added support for "active high" and "active low" latches in read_blif and write_blif + - Use init value "2" for all uninitialized FFs in BLIF back-end + - Added "read_blif -sop" + - Added "write_blif -noalias" + - Added various write_blif options for VTR support + - write_json: also write module attributes. + - Added "write_verilog -nodec -nostr -defparam" + - Added "read_verilog -norestrict -assume-asserts" + - Added support for bus interfaces to "read_liberty -lib" + - Added liberty parser support for types within cell decls + - Added "write_verilog -renameprefix -v" + - Added "write_edif -nogndvcc" + + * Formal Verification + - Support for hierarchical designs in smt2 back-end + - Yosys-smtbmc: Support for hierarchical VCD dumping + - Added $initstate cell type and vlog function + - Added $anyconst and $anyseq cell types and vlog functions + - Added printing of code loc of failed asserts to yosys-smtbmc + - Added memory_memx pass, "memory -memx", and "prep -memx" + - Added "proc_mux -ifx" + - Added "yosys-smtbmc -g" + - Deprecated "write_smt2 -regs" (by default on now) + - Made "write_smt2 -bv -mem" default, added "write_smt2 -nobv -nomem" + - Added support for memories to smtio.py + - Added "yosys-smtbmc --dump-vlogtb" + - Added "yosys-smtbmc --smtc --dump-smtc" + - Added "yosys-smtbmc --dump-all" + - Added assertpmux command + - Added "yosys-smtbmc --unroll" + - Added $past, $stable, $rose, $fell SVA functions + - Added "yosys-smtbmc --noinfo and --dummy" + - Added "yosys-smtbmc --noincr" + - Added "yosys-smtbmc --cex " + - Added $ff and $_FF_ cell types + - Added $global_clock verilog syntax support for creating $ff cells + - Added clk2fflogic + + +Yosys 0.5 .. Yosys 0.6 +---------------------- + + * Various + - Added Contributor Covenant Code of Conduct + - Various improvements in dict<> and pool<> + - Added hashlib::mfp and refactored SigMap + - Improved support for reals as module parameters + - Various improvements in SMT2 back-end + - Added "keep_hierarchy" attribute + - Verilog front-end: define `BLACKBOX in -lib mode + - Added API for converting internal cells to AIGs + - Added ENABLE_LIBYOSYS Makefile option + - Removed "techmap -share_map" (use "-map +/filename" instead) + - Switched all Python scripts to Python 3 + - Added support for $display()/$write() and $finish() to Verilog front-end + - Added "yosys-smtbmc" formal verification flow + - Added options for clang sanitizers to Makefile + + * New commands and options + - Added "scc -expect -nofeedback" + - Added "proc_dlatch" + - Added "check" + - Added "select %xe %cie %coe %M %C %R" + - Added "sat -dump_json" (WaveJSON format) + - Added "sat -tempinduct-baseonly -tempinduct-inductonly" + - Added "sat -stepsize" and "sat -tempinduct-step" + - Added "sat -show-regs -show-public -show-all" + - Added "write_json" (Native Yosys JSON format) + - Added "write_blif -attr" + - Added "dffinit" + - Added "chparam" + - Added "muxcover" + - Added "pmuxtree" + - Added memory_bram "make_outreg" feature + - Added "splice -wires" + - Added "dff2dffe -direct-match" + - Added simplemap $lut support + - Added "read_blif" + - Added "opt_share -share_all" + - Added "aigmap" + - Added "write_smt2 -mem -regs -wires" + - Added "memory -nordff" + - Added "write_smv" + - Added "synth -nordff -noalumacc" + - Added "rename -top new_name" + - Added "opt_const -clkinv" + - Added "synth -nofsm" + - Added "miter -assert" + - Added "read_verilog -noautowire" + - Added "read_verilog -nodpi" + - Added "tribuf" + - Added "lut2mux" + - Added "nlutmap" + - Added "qwp" + - Added "test_cell -noeval" + - Added "edgetypes" + - Added "equiv_struct" + - Added "equiv_purge" + - Added "equiv_mark" + - Added "equiv_add -try -cell" + - Added "singleton" + - Added "abc -g -luts" + - Added "torder" + - Added "write_blif -cname" + - Added "submod -copy" + - Added "dffsr2dff" + - Added "stat -liberty" + + * Synthesis metacommands + - Various improvements in synth_xilinx + - Added synth_ice40 and synth_greenpak4 + - Added "prep" metacommand for "synthesis lite" + + * Cell library changes + - Added cell types to "help" system + - Added $meminit cell type + - Added $assume cell type + - Added $_MUX4_, $_MUX8_, and $_MUX16_ cells + - Added $tribuf and $_TBUF_ cell types + - Added read-enable to memory model + + * YosysJS + - Various improvements in emscripten build + - Added alternative webworker-based JS API + - Added a few example applications + + +Yosys 0.4 .. Yosys 0.5 +---------------------- + + * API changes + - Added log_warning() + - Added eval_select_args() and eval_select_op() + - Added cell->known(), cell->input(portname), cell->output(portname) + - Skip blackbox modules in design->selected_modules() + - Replaced std::map<> and std::set<> with dict<> and pool<> + - New SigSpec::extend() is what used to be SigSpec::extend_u0() + - Added YS_OVERRIDE, YS_FINAL, YS_ATTRIBUTE, YS_NORETURN + + * Cell library changes + - Added flip-flops with enable ($dffe etc.) + - Added $equiv cells for equivalence checking framework + + * Various + - Updated ABC to hg rev 61ad5f908c03 + - Added clock domain partitioning to ABC pass + - Improved plugin building (see "yosys-config --build") + - Added ENABLE_NDEBUG Makefile flag for high-performance builds + - Added "yosys -d", "yosys -L" and other driver improvements + - Added support for multi-bit (array) cell ports to "write_edif" + - Now printing most output to stdout, not stderr + - Added "onehot" attribute (set by "fsm_map") + - Various performance improvements + - Vastly improved Xilinx flow + - Added "make unsintall" + + * Equivalence checking + - Added equivalence checking commands: + equiv_make equiv_simple equiv_status + equiv_induct equiv_miter + equiv_add equiv_remove + + * Block RAM support: + - Added "memory_bram" command + - Added BRAM support to Xilinx flow + + * Other New Commands and Options + - Added "dff2dffe" + - Added "fsm -encfile" + - Added "dfflibmap -prepare" + - Added "write_blid -unbuf -undef -blackbox" + - Added "write_smt2" for writing SMT-LIBv2 files + - Added "test_cell -w -muxdiv" + - Added "select -read" + + +Yosys 0.3.0 .. Yosys 0.4 +------------------------ + + * Platform Support + - Added support for mxe-based cross-builds for win32 + - Added sourcecode-export as VisualStudio project + - Added experimental EMCC (JavaScript) support + + * Verilog Frontend + - Added -sv option for SystemVerilog (and automatic *.sv file support) + - Added support for real-valued constants and constant expressions + - Added support for non-standard "via_celltype" attribute on task/func + - Added support for non-standard "module mod_name(...);" syntax + - Added support for non-standard """ macro bodies + - Added support for array with more than one dimension + - Added support for $readmemh and $readmemb + - Added support for DPI functions + + * Changes in internal cell library + - Added $shift and $shiftx cell types + - Added $alu, $lcu, $fa and $macc cell types + - Removed $bu0 and $safe_pmux cell types + - $mem/$memwr WR_EN input is now a per-data-bit enable signal + - Added $_NAND_ $_NOR_ $_XNOR_ $_AOI3_ $_OAI3_ $_AOI4_ $_OAI4_ + - Renamed ports of $lut cells (from I->O to A->Y) + - Renamed $_INV_ to $_NOT_ + + * Changes for simple synthesis flows + - There is now a "synth" command with a recommended default script + - Many improvements in synthesis of arithmetic functions to gates + - Multipliers and adders with many operands are using carry-save adder trees + - Remaining adders are now implemented using Brent-Kung carry look-ahead adders + - Various new high-level optimizations on RTL netlist + - Various improvements in FSM optimization + - Updated ABC to hg 5b5af75f1dda (from 2014-11-07) + + * Changes in internal APIs and RTLIL + - Added log_id() and log_cell() helper functions + - Added function-like cell creation helpers + - Added GetSize() function (like .size() but with int) + - Major refactoring of RTLIL::Module and related classes + - Major refactoring of RTLIL::SigSpec and related classes + - Now RTLIL::IdString is essentially an int + - Added macros for code coverage counters + - Added some Makefile magic for pretty make logs + - Added "kernel/yosys.h" with all the core definitions + - Changed a lot of code from FILE* to c++ streams + - Added RTLIL::Monitor API and "trace" command + - Added "Yosys" C++ namespace + + * Changes relevant to SAT solving + - Added ezSAT::keep_cnf() and ezSAT::non_incremental() + - Added native ezSAT support for vector shift ops + - Updated MiniSAT to git 37dc6c67e2 (from 2013-09-25) + + * New commands (or large improvements to commands) + - Added "synth" command with default script + - Added "share" (finally some real resource sharing) + - Added "memory_share" (reduce number of ports on memories) + - Added "wreduce" and "alumacc" commands + - Added "opt -keepdc -fine -full -fast" + - Added some "test_*" commands + + * Various other changes + - Added %D and %c select operators + - Added support for labels in yosys scripts + - Added support for here-documents in yosys scripts + - Support "+/" prefix for files from proc_share_dir + - Added "autoidx" statement to ilang language + - Switched from "yosys-svgviewer" to "xdot" + - Renamed "stdcells.v" to "techmap.v" + - Various bug fixes and small improvements + - Improved welcome and bye messages + + +Yosys 0.2.0 .. Yosys 0.3.0 -------------------------- * Driver program and overall behavior: @@ -43,7 +491,7 @@ Yosys 0.2.0 .. Yoys 0.3.0 - Added "sat -dump_cnf" feature - Added "sat -initsteps " feature - Added "freduce -stop " feature - - Added "fredure -dump " feature + - Added "freduce -dump " feature * Integration with ABC: - Updated ABC rev to 7600ffb9340c @@ -53,8 +501,8 @@ Yosys 0.2.0 .. Yoys 0.3.0 - Various build fixes for OSX (Darwin) and OpenBSD -Yosys 0.1.0 .. Yoys 0.2.0 -------------------------- +Yosys 0.1.0 .. Yosys 0.2.0 +-------------------------- * Changes to the driver program: - Added "yosys -h" and "yosys -H" @@ -130,13 +578,13 @@ Yosys 0.1.0 .. Yoys 0.2.0 - Added "expose" command - Added support for @ to sat and eval signal expressions - * Changes in the 'make test' framework and auxilary test tools: + * Changes in the 'make test' framework and auxiliary test tools: - Added autotest.sh -p and -f options - Replaced autotest.sh ISIM support with XSIM support - Added test cases for SAT framework * Added "abbreviated IDs": - - Now $$foo can be abbriviated as $foo. + - Now $$foo can be abbreviated as $foo. - Usually this last part is a unique id (from RTLIL::autoidx) - This abbreviated IDs are now also used in "show" output