X-Git-Url: https://git.libre-soc.org/?a=blobdiff_plain;f=CHANGELOG;h=a27adc5bff0333995c6e6da133c9f27d2bbc40e0;hb=9c69e9f8a60180f61e4ca8de9887e98e231dc043;hp=0b1bbc733b8e01fa09489c2a6d3f1c13d950a9f3;hpb=d1fbe738a76efbdbb04da7d8aa04d19d54d6e9cd;p=yosys.git

diff --git a/CHANGELOG b/CHANGELOG
index 0b1bbc733..a27adc5bf 100644
--- a/CHANGELOG
+++ b/CHANGELOG
@@ -2,7 +2,26 @@
 List of major changes and improvements between releases
 =======================================================
 
-Yosys 0.14 .. Yosys 0.14-dev
+Yosys 0.16 .. Yosys 0.16-dev
+--------------------------
+
+ * SystemVerilog
+    - Fixed automatic `nosync` inference for local variables in `always_comb`
+      procedures not applying to nested blocks and blocks in functions
+
+Yosys 0.15 .. Yosys 0.16
+--------------------------
+ * Various
+    - Added BTOR2 witness file co-simulation.
+    - Simulation calls external vcd2fst for VCD conversion.
+    - Added fst2tb pass - generates testbench for the circuit using
+      the given top-level module and simulus signal from FST file.
+    - yosys-smtbmc: Option to keep going after failed assertions in BMC mode
+
+ * Verific support
+    - Import modules in alphabetic (reproducable) order.
+
+Yosys 0.14 .. Yosys 0.15
 --------------------------
 
  * Various