X-Git-Url: https://git.libre-soc.org/?a=blobdiff_plain;f=Cesar_Strauss.mdwn;h=e1ca0783d5d8abdbb206262230adb835691a4c17;hb=112d5247fa47aa15e039510263e5a74c9ee856d9;hp=683c27adb1f017ec0f7dd4e94bcf78f3e509b5ab;hpb=fe64356f82d0f5c5f9ee4be4548a897647b71a43;p=libreriscv.git

diff --git a/Cesar_Strauss.mdwn b/Cesar_Strauss.mdwn
index 683c27adb..e1ca0783d 100644
--- a/Cesar_Strauss.mdwn
+++ b/Cesar_Strauss.mdwn
@@ -71,9 +71,30 @@ unit tests.
 
 ## Submitted for NLNet RFP
 
+### NLnet.2019.02.012
+
+* [Bug #583](https://bugs.libre-soc.org/show_bug.cgi?id=583):
+  Implement simple VL for\-loop in nMigen for TestIssuer
+    * €2325 which is the total amount
+    * submitted on 2022-06-16
+
+### NLNet.2019.10.032.Formal
+
+* [Bug #565](https://bugs.libre-soc.org/show_bug.cgi?id=565):
+  Improve formal verification on PartitionedSignal
+    * €2200 out of total of €3000
+    * submitted on 2022-06-16
+
+### NLNet.2019.10.046.Standards
+
+* [Bug #588](https://bugs.libre-soc.org/show_bug.cgi?id=588):
+  add SVP64 to PowerDecoder2
+    * €300 out of total of €1000
+    * submitted on 2022-06-16
+
 ## Paid
 
-### NLNet.2019.10.Wishbone
+### NLNet.2019.10.043.Wishbone
 
 * [Bug #475](https://bugs.libre-soc.org/show_bug.cgi?id=475):
   cxxsim improvements