X-Git-Url: https://git.libre-soc.org/?a=blobdiff_plain;f=Cesar_Strauss.mdwn;h=e1ca0783d5d8abdbb206262230adb835691a4c17;hb=9f37111eb74b3ca2505cdc12b0f701a7405b37c1;hp=6a6279401da0f5bf1890eb9deb4204721a0717d8;hpb=de1a8dedddb7884aacd5f07ef83eb341e1aa8945;p=libreriscv.git

diff --git a/Cesar_Strauss.mdwn b/Cesar_Strauss.mdwn
index 6a6279401..e1ca0783d 100644
--- a/Cesar_Strauss.mdwn
+++ b/Cesar_Strauss.mdwn
@@ -50,20 +50,56 @@ unit tests.
 	<https://bugs.libre-soc.org/show_bug.cgi?id=350>  
 	Priority: Medium-ish
 
-10. Find root cause of cxxsim hang  
-	<https://bugs.libre-soc.org/show_bug.cgi?id=475#c2>  
-	Status: ongoing  
-	Priority: High
-
-11. Formal Proof for CompUnit
+11. Formal Proof for CompUnit  
         <https://bugs.libre-soc.org/show_bug.cgi?id=342>
 
+12. Formal Proof for PartitionedSignal  
+        <https://bugs.libre-soc.org/show_bug.cgi?id=565>  
+        Status: in progress  
+
+13. Implement simple VL for-loop in nMigen for TestIssuer  
+        <https://bugs.libre-soc.org/show_bug.cgi?id=583>  
+        Status: in progress  
 
 ## Completed but not yet submitted:
 
 1. FSM-based ALU example needed (compliant with ALU CompUnit)  
 	<https://bugs.libre-soc.org/show_bug.cgi?id=417>  
-	
+
+2. Fix MSB0 issues in the SVP64 Assembler, Simulator and Decoder  
+	<https://bugs.libre-soc.org/show_bug.cgi?id=600>
+
 ## Submitted for NLNet RFP
 
+### NLnet.2019.02.012
+
+* [Bug #583](https://bugs.libre-soc.org/show_bug.cgi?id=583):
+  Implement simple VL for\-loop in nMigen for TestIssuer
+    * &euro;2325 which is the total amount
+    * submitted on 2022-06-16
+
+### NLNet.2019.10.032.Formal
+
+* [Bug #565](https://bugs.libre-soc.org/show_bug.cgi?id=565):
+  Improve formal verification on PartitionedSignal
+    * &euro;2200 out of total of &euro;3000
+    * submitted on 2022-06-16
+
+### NLNet.2019.10.046.Standards
+
+* [Bug #588](https://bugs.libre-soc.org/show_bug.cgi?id=588):
+  add SVP64 to PowerDecoder2
+    * &euro;300 out of total of &euro;1000
+    * submitted on 2022-06-16
+
 ## Paid
+
+### NLNet.2019.10.043.Wishbone
+
+* [Bug #475](https://bugs.libre-soc.org/show_bug.cgi?id=475):
+  cxxsim improvements
+    * Ran several Libre-SOC tests under cxxsim
+    * Helped isolate simulator issues by extracting a MVCE
+(Minimal, Verifiable, Complete Example) in each case.
+    * paid on 2021-05-11
+    * &euro;250 out of total of &euro;1750