X-Git-Url: https://git.libre-soc.org/?a=blobdiff_plain;f=HDL_workflow.mdwn;h=94e9ed30ee9a6c1e27350487371b9ec5fd2f774d;hb=5d461c6aa24890ecd847d87a8c6aa891ed15b7e0;hp=3118e4e1eb14c2ed14f2d42baaf49950698a625e;hpb=28999f2ea18f0f5797e8799f50b7df942b8bab6f;p=libreriscv.git diff --git a/HDL_workflow.mdwn b/HDL_workflow.mdwn index 3118e4e1e..94e9ed30e 100644 --- a/HDL_workflow.mdwn +++ b/HDL_workflow.mdwn @@ -294,7 +294,7 @@ root prompt, and save yourself some typing. * sudo bash * apt-get install vim exuberant-ctags * apt-get install build-essential -* apt-get install git python3.7 python3.7-dev python-nosetest3 +* apt-get install git python3.7 python3.7-dev python3-nose * apt-get install graphviz xdot gtkwave * apt-get install python3-venv * apt-get install python-virtualenv # this is an alternative to python3-venv @@ -340,11 +340,15 @@ and that people communicate and coordinate with each other. This is not a hard rule: under special cirmstances branches can be useful. They should not however be considered "routine". +For advice on commit messages see +[here](https://tbaggery.com/2008/04/19/a-note-about-git-commit-messages.html), +and [here](https://github.com/torvalds/subsurface-for-dirk/blob/master/README.md#contributing)). + ## yosys Follow the source code (git clone) instructions here, do **not** use the "stable" version (do not download the tarball): - + Or, alternatively, use the [hdl-tools-yosys](https://git.libre-soc.org/?p=dev-env-setup.git;a=blob;f=hdl-tools-yosys;hb=HEAD) @@ -353,7 +357,7 @@ script (which also installs symbiyosys and its dependencies) Do not try to use a fixed revision of yosys (currently 0.9), nmigen is evolving and frequently interacts with yosys. -[Yosys](http://www.clifford.at/yosys/) is a framework for Verilog RTL. +[Yosys](https://github.com/YosysHQ/yosys is a framework for Verilog RTL. [Verilog](https://en.wikipedia.org/wiki/Verilog) is a hardware description language. RTL [Register Transfer @@ -377,7 +381,9 @@ circumstances). front-end driver program for Yosys-based formal hardware verification flows. -## nmigen +## nmigen (TM) + +*nmigen is a registered trademark of M-Labs * **PLEASE NOTE: it is critical to install nmigen as the first dependency prior to installing any further python-based Libre-SOC HDL repositories. @@ -387,7 +393,7 @@ If "pip3 list" shows that nmigen has been auto-installed please remove it** * mkdir ~/src * cd !$ -* git clone https://github.com/nmigen/nmigen.git +* git clone https://gitlab.com/nmigen/nmigen.git * cd nmigen * sudo bash * python3 setup.py develop @@ -439,7 +445,7 @@ In the meantime, sfpy can be built as follows: You can test your installation by doing the following: python3 - >>> from sfpy import * + >>> from sfpy import Posit8 >>> Posit8(1.3) It should print out `Posit8(1.3125)` @@ -543,7 +549,18 @@ See [[HDL_workflow/coriolis2]] page, for those people doing layout work. A portable FPGA place and route tool. -See [[HDL_workflow/nextpnr]] page for installation instructions of nextpnr with ECP5 support for Lattice FPGA ECP5 series. +See [[HDL_workflow/nextpnr]] page for installation instructions of nextpnr with ECP5 support for Lattice FPGA ECP5 series. Also see +[[HDL_workflow/ECP5_FPGA]] for connecting up to JTAG with a ULX3S +and the Lattice VERSA_ECP5. + +## Nextpnr-xilinx + +An open source place and route framework for Xilinx FPGAs using Project Xray. We will use it for Xilinx 7-series FPGAs like Artix-7. + +One of the ways to get Arty A7 100t Digilent FPGA board working. + +See [[HDL_workflow/nextpnr-xilinx]] for installation instructions and dependencies. + ## Verilator @@ -579,10 +596,26 @@ See [[HDL_workflow/cocotb]] page for installation instructions. ## Symbiflow -needed for the Arty A7 100t Digilent FPGA board +A fully open source toolchain for the development of FPGAs. Currently it targets Xilinx 7-series, Lattice iCE40 and ECP5, Quicklogic EOS S3. + +One way to get the Arty A7 100t Digilent FPGA board working. See [[HDL_workflow/symbiflow]] for installation instructions -and dependencies +and dependencies. + +## FPGA/Board Boot-Loaders-Programmers + +Open source FPGA/Board boot-loaders and programmers for ULX3S, ECP5 and +OrangeCrab. + +Currently these programs dfu-util, openFPGALoader, ujprog, fujprog, +xc3sprog and ecpprog are going to be used. + +See [[HDL_workflow/fpga-boot-loaders-progs]] for installation instructions and dependencies. + +## ls2 peripheral fabric + +[[HDL_workflow/ls2]] # Registering for git repository access @@ -655,17 +688,23 @@ Before running the following, install the dependencies. This is easiest done with this script +**It is critically important to install these in STRICT order, otherwise +pip3 interferes and performs unauthorised downloads without informing +you of what it is doing**. + * mkdir ~/src * cd !$ -* git clone gitolite3@git.libre-soc.org:nmigen.git +* git clone https://gitlab.com/nmigen/nmigen +* git clone https://gitlab.com/nmigen/nmigen-boards +* git clone https://gitlab.com/nmigen/nmigen-soc +* git clone https://gitlab.com/nmigen/nmigen-stdio * git clone gitolite3@git.libre-soc.org:c4m-jtag.git * git clone gitolite3@git.libre-soc.org:nmutil.git * git clone gitolite3@git.libre-soc.org:openpower-isa.git * git clone gitolite3@git.libre-soc.org:ieee754fpu.git -* git clone gitolite3@git.libre-soc.org:nmigen-soc.git * git clone gitolite3@git.libre-soc.org:soc.git -In each of these directories, in the order listed, track down the +In each of these directories, **in the order listed**, track down the `setup.py` file, then, as root (`sudo bash`), run the following: * python3 setup.py develop @@ -676,7 +715,9 @@ for multi-user machine use however it is often just easier to get your own machine these days. The reason for the order is because soc depends on ieee754fpu, and -ieee754fpu depends on nmutil +ieee754fpu depends on nmutil. If you do not follow the listed order +pip3 will go off and download an arbitrary version without your +consent. If "`python3 setup.py install`" is used it is a pain: edit, then install. edit, then install. It gets extremely tedious, hence why @@ -917,6 +958,11 @@ the double import of the class from two separate locations, immediately. Really. don't. use. wildcards. +More about this here: + +* +* + ### Keep file and variables short but clear * try to keep both filenames and variable names short but not ridiculously @@ -1063,6 +1109,42 @@ Simply mark it with an appropriate preferably with a link to a URL in the [bugtracker](https://bugs.libre-soc.org/) with further details as to why the unit test should not be run. +# Task management guidelines + +1. Create the task in appropriate "Product" section with appropriate + "Component" section. Most code tasks generally use "Libre-SOC's + first SOC". +2. Fill in "Depends on" and "Blocks" section whenever appropriate. + Also add as many related ("See Also") links to other bugreports + as possible. bugreports are never isolated. +3. Choose the correct task for a budget allocation. Usually the parent + task is used. +4. Choose the correct NLnet milestone. The best practice is to check + the parent task for a correct milestone. +5. Assign the budget to the task in `"USER=SUM"` form, where "USER" + corresponds to your username and "SUM" corresponds to the actual + budget in EUR. There may be multiple users. +6. When the task is completed, you can begin writing an RFP. + **DO NOT submit it without explicit authorisation and review**. + Leave out your bank and personal address details if you prefer + when sending to the Team Manager for review. +7. Once the RFP is written, notify the Team Manager and obtain their + explicit approval to send it. +8. Once approval is received and the RFP sent, update the `"USER=SUM"` + field to include the submitted date: + `"USER={amount=SUM, submitted=SDATE}"`. The SDATE is entered in + `YYYY-MM-DD` form. +9. Once the task is paid, again notify the Team Manager (IRC is fine), + and update `"USER={amount=SUM, submitted=SDATE}"` + to `"USER={amount=SUM, submitted=SDATE, paid=PDATE}"`. The PDATE is + entered in `YYYY-MM-DD` form, too. + +Throughout all of this you should be using budget-sync to check the +database consistency + + +[[!img bugzilla_RFP_fields.jpg size=640x ]] + # TODO Tutorials Find appropriate tutorials for nmigen and yosys, as well as symbiyosys. @@ -1076,6 +1158,6 @@ Find appropriate tutorials for nmigen and yosys, as well as symbiyosys. and walks not just through simulation, it takes you through using gtkwave as well. * There exist several nmigen examples which are also executable - exactly as + exactly as described in the above tutorial (python3 filename.py -h) * More nmigen tutorials at [[learning_nmigen]]