X-Git-Url: https://git.libre-soc.org/?a=blobdiff_plain;f=Makefile;h=3d4ea62db5a779f896d1f59665014783681f0523;hb=006a05dbea6682535341b8d6be5627f2733d3ead;hp=b7d73ee58c280d298136d9773db7bffa972747c9;hpb=e59237af023bd68da314fc06dba5ac571aec0369;p=soc.git diff --git a/Makefile b/Makefile index b7d73ee5..3d4ea62d 100644 --- a/Makefile +++ b/Makefile @@ -11,13 +11,15 @@ mkpinmux: cp pinmux/ls180/ls180_pins.py src/soc/debug cp pinmux/ls180/ls180_pins.py src/soc/litex/florent/libresoc -install: gitupdate develop mkpinmux svanalysis +install: gitupdate develop mkpinmux +# this is now actually part of openpower-isa repository pywriter: - python3 src/soc/decoder/pseudo/pywriter.py + echo "pywriter is part of openpower-isa, run that instead" +# this is now actually part of openpower-isa repository svanalysis: - python3 libreriscv/openpower/sv_analysis.py + echo "sv_analysis is part of openpower-isa, run that instead" develop: python3 setup.py develop # yes, develop, not install @@ -36,6 +38,12 @@ testgpio_run_sim: python3 src/soc/litex/florent/sim.py --cpu=libresoc \ --variant=standardjtagtestgpio +ls180_verilog_nopll: + python3 src/soc/simple/issuer_verilog.py \ + --debug=jtag --enable-core --disable-pll \ + --enable-xics --disable-svp64 \ + src/soc/litex/florent/libresoc/libresoc.v + ls180_verilog: python3 src/soc/simple/issuer_verilog.py \ --debug=jtag --enable-core --enable-pll \ @@ -49,8 +57,8 @@ ls180_4k_verilog: src/soc/litex/florent/libresoc/libresoc.v # build the litex libresoc SoC without 4k SRAMs -ls180_4ksram_verilog_build: ls180_verilog - make -C soc/soc/litex/florent ls1804k +ls180_verilog_build: ls180_verilog + make -C soc/soc/litex/florent ls180 # build the litex libresoc SoC with 4k SRAMs ls180_4ksram_verilog_build: ls180_4k_verilog @@ -60,6 +68,9 @@ ls180_4ksram_verilog_build: ls180_4k_verilog test: install python3 setup.py test # could just run nosetest3... +pypiupload: + $(PYTHON3) setup.py sdist upload + # Minimal makefile for Sphinx documentation #