X-Git-Url: https://git.libre-soc.org/?a=blobdiff_plain;f=Makefile;h=909a463a0d605f97d2c931c5e65015ca1d1b1406;hb=32b0d64c91ac2830e6526f1a020c9402fb208ad0;hp=abb446dd00b02008e36f3412235f37be5194d312;hpb=434ee06553fc53e46da2282d7017fa68dfa4fb13;p=soc.git

diff --git a/Makefile b/Makefile
index abb446dd..909a463a 100644
--- a/Makefile
+++ b/Makefile
@@ -13,11 +13,13 @@ mkpinmux:
 
 install: gitupdate develop mkpinmux svanalysis
 
+# this is now actually part of openpower-isa repository
 pywriter:
-	python3 src/soc/decoder/pseudo/pywriter.py
+	pywriter
 
+# this is now actually part of openpower-isa repository
 svanalysis:
-	python3 libreriscv/openpower/sv_analysis.py
+	svanalysis
 
 develop:
 	python3 setup.py develop # yes, develop, not install
@@ -36,6 +38,12 @@ testgpio_run_sim:
 	python3 src/soc/litex/florent/sim.py --cpu=libresoc \
 			--variant=standardjtagtestgpio
 
+ls180_verilog_nopll:
+	python3 src/soc/simple/issuer_verilog.py \
+	        --debug=jtag --enable-core --disable-pll \
+	        --enable-xics --disable-svp64 \
+			src/soc/litex/florent/libresoc/libresoc.v
+
 ls180_verilog:
 	python3 src/soc/simple/issuer_verilog.py \
 	        --debug=jtag --enable-core --enable-pll \
@@ -60,6 +68,9 @@ ls180_4ksram_verilog_build: ls180_4k_verilog
 test: install
 	python3 setup.py test # could just run nosetest3...
 
+pypiupload:
+	$(PYTHON3) setup.py sdist upload
+
 # Minimal makefile for Sphinx documentation
 #