X-Git-Url: https://git.libre-soc.org/?a=blobdiff_plain;f=Makefile;h=d8db01ffe6547324b0c0c0b817bcb28b97a4a70c;hb=HEAD;hp=2ee5d572ceffc4bfa99b86d2cb63c06d2ac017a6;hpb=081dc64d39a150677ab37e711a5bfff980370bb3;p=microwatt.git diff --git a/Makefile b/Makefile index 2ee5d57..d8db01f 100644 --- a/Makefile +++ b/Makefile @@ -1,6 +1,9 @@ GHDL ?= ghdl -GHDLFLAGS=--std=08 -frelaxed +GHDLFLAGS=--std=08 CFLAGS=-O3 -Wall +VERILATOR_FLAGS=-O3 #--trace +# It takes forever to build with optimisation, so disable by default +#VERILATOR_CFLAGS=-O3 GHDLSYNTH ?= ghdl.so YOSYS ?= yosys @@ -43,20 +46,20 @@ all: $(all) core_files = decode_types.vhdl common.vhdl wishbone_types.vhdl fetch1.vhdl \ utils.vhdl plru.vhdl cache_ram.vhdl icache.vhdl \ - decode1.vhdl helpers.vhdl insn_helpers.vhdl gpr_hazard.vhdl \ - cr_hazard.vhdl control.vhdl decode2.vhdl register_file.vhdl \ + decode1.vhdl helpers.vhdl insn_helpers.vhdl \ + control.vhdl decode2.vhdl register_file.vhdl \ cr_file.vhdl crhelpers.vhdl ppc_fx_insns.vhdl rotator.vhdl \ logical.vhdl countzero.vhdl multiply.vhdl divider.vhdl execute1.vhdl \ loadstore1.vhdl mmu.vhdl dcache.vhdl writeback.vhdl core_debug.vhdl \ core.vhdl fpu.vhdl -soc_files = $(core_files) wishbone_arbiter.vhdl wishbone_bram_wrapper.vhdl sync_fifo.vhdl \ +soc_files = wishbone_arbiter.vhdl wishbone_bram_wrapper.vhdl sync_fifo.vhdl \ wishbone_debug_master.vhdl xics.vhdl syscon.vhdl soc.vhdl \ spi_rxtx.vhdl spi_flash_ctrl.vhdl uart_files = $(wildcard uart16550/*.v) -soc_sim_files = $(soc_files) sim_console.vhdl sim_pp_uart.vhdl sim_bram_helpers.vhdl \ +soc_sim_files = $(core_files) $(soc_files) sim_console.vhdl sim_pp_uart.vhdl sim_bram_helpers.vhdl \ sim_bram.vhdl sim_jtag_socket.vhdl sim_jtag.vhdl dmi_dtm_xilinx.vhdl \ sim_16550_uart.vhdl \ random.vhdl glibc_random.vhdl glibc_random_helpers.vhdl @@ -115,10 +118,8 @@ $(soc_dram_tbs): $(error "Verilator is required to make this target !") else -VERILATOR_CFLAGS=-O3 -VERILATOR_FLAGS=-O3 verilated_dram: litedram/generated/sim/litedram_core.v - verilator $(VERILATOR_FLAGS) -CFLAGS $(VERILATOR_CFLAGS) -Wno-fatal --cc $< --trace + verilator $(VERILATOR_FLAGS) -CFLAGS $(VERILATOR_CFLAGS) -Wno-fatal --cc $< make -C obj_dir -f ../litedram/extras/sim_dram_verilate.mk VERILATOR_ROOT=$(VERILATOR_ROOT) SIM_DRAM_CFLAGS = -I. -Iobj_dir -Ilitedram/generated/sim -I$(VERILATOR_ROOT)/include -I$(VERILATOR_ROOT)/include/vltstd @@ -126,7 +127,7 @@ SIM_DRAM_CFLAGS += -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TRACE=1 -DVL_PRINTF=printf -fa sim_litedram_c.o: litedram/extras/sim_litedram_c.cpp verilated_dram $(CC) $(CPPFLAGS) $(SIM_DRAM_CFLAGS) $(CFLAGS) -c $< -o $@ -soc_dram_files = $(soc_files) litedram/extras/litedram-wrapper-l2.vhdl litedram/generated/sim/litedram-initmem.vhdl +soc_dram_files = $(core_files) $(soc_files) litedram/extras/litedram-wrapper-l2.vhdl litedram/generated/sim/litedram-initmem.vhdl soc_dram_sim_files = $(soc_sim_files) litedram/extras/sim_litedram.vhdl soc_dram_sim_obj_files = $(soc_sim_obj_files) sim_litedram_c.o dram_link_files=-Wl,obj_dir/Vlitedram_core__ALL.a -Wl,obj_dir/verilated.o -Wl,obj_dir/verilated_vcd_c.o -Wl,-lstdc++ @@ -170,11 +171,44 @@ OPENOCD_JTAG_CONFIG=openocd/ecp5-evn.cfg OPENOCD_DEVICE_CONFIG=openocd/LFE5UM5G-85F.cfg endif +# Arctic Tern with ECP85 +ifeq ($(FPGA_TARGET), ARCTIC-TERN) +RESET_LOW=true +CLK_INPUT=125000000 +CLK_FREQUENCY=48000000 +LPF=constraints/arctic-tern.lpf +PACKAGE=CABGA381 +NEXTPNR_FLAGS=--um5g-85k --freq 48 --ignore-loops +OPENOCD_JTAG_CONFIG=openocd/olimex-arm-usb-tiny-h.cfg +OPENOCD_DEVICE_CONFIG=openocd/LFE5UM5G-85F.cfg +toplevel=fpga/top-rcs-arctic-tern-bmc-card.vhdl +soc_files += litedram/extras/litedram-wrapper-l2.vhdl \ + litedram/generated/rcs-arctic-tern-bmc-card/litedram-initmem.vhdl +soc_extra_v += litedram/generated/rcs-arctic-tern-bmc-card/litedram_core.v +soc_extra_v += liteeth/generated/rcs-arctic-tern-bmc-card/liteeth_core.v +soc_extra_v += pinyon/wishbone_interface.v +soc_extra_v += tercel/phy.v +soc_extra_v += tercel/wishbone_spi_master.v +soc_extra_v += aquila/io_blocks.v +soc_extra_v += aquila/lpc_slave.v +soc_extra_v += aquila/wishbone_lpc_slave_interface.v +soc_extra_v += aquila/third_party/async_fifo/async_bidir_fifo.v +soc_extra_v += aquila/third_party/async_fifo/async_bidir_ramif_fifo.v +soc_extra_v += aquila/third_party/async_fifo/async_fifo.v +soc_extra_v += aquila/third_party/async_fifo/fifo_2mem.v +soc_extra_v += aquila/third_party/async_fifo/fifomem_dp.v +soc_extra_v += aquila/third_party/async_fifo/rptr_empty.v +soc_extra_v += aquila/third_party/async_fifo/sync_ptr.v +soc_extra_v += aquila/third_party/async_fifo/sync_r2w.v +soc_extra_v += aquila/third_party/async_fifo/sync_w2r.v +soc_extra_v += aquila/third_party/async_fifo/wptr_full.v +endif + GHDL_IMAGE_GENERICS=-gMEMORY_SIZE=$(MEMORY_SIZE) -gRAM_INIT_FILE=$(RAM_INIT_FILE) \ -gRESET_LOW=$(RESET_LOW) -gCLK_INPUT=$(CLK_INPUT) -gCLK_FREQUENCY=$(CLK_FREQUENCY) clkgen=fpga/clk_gen_ecp5.vhd -toplevel=fpga/top-generic.vhdl +toplevel ?= fpga/top-generic.vhdl dmi_dtm=dmi_dtm_dummy.vhdl ifeq ($(FPGA_TARGET), verilator) @@ -184,21 +218,21 @@ CLK_FREQUENCY=50000000 clkgen=fpga/clk_gen_bypass.vhd endif -fpga_files = $(core_files) $(soc_files) fpga/soc_reset.vhdl \ +fpga_files = fpga/soc_reset.vhdl \ fpga/pp_fifo.vhd fpga/pp_soc_uart.vhd fpga/main_bram.vhdl \ nonrandom.vhdl synth_files = $(core_files) $(soc_files) $(fpga_files) $(clkgen) $(toplevel) $(dmi_dtm) microwatt.json: $(synth_files) $(RAM_INIT_FILE) - $(YOSYS) -m $(GHDLSYNTH) -p "ghdl --std=08 --no-formal $(GHDL_IMAGE_GENERICS) $(GHDL_TARGET_GENERICS) $(synth_files) -e toplevel; synth_ecp5 -json $@ $(SYNTH_ECP5_FLAGS)" $(uart_files) + $(YOSYS) -m $(GHDLSYNTH) -p "ghdl --std=08 --no-formal $(GHDL_IMAGE_GENERICS) $(synth_files) -e toplevel; read_verilog $(uart_files) $(soc_extra_v); synth_ecp5 -json $@ $(SYNTH_ECP5_FLAGS)" $(uart_files) microwatt.v: $(synth_files) $(RAM_INIT_FILE) - $(YOSYS) -m $(GHDLSYNTH) -p "ghdl --std=08 --no-formal $(GHDL_IMAGE_GENERICS) $(GHDL_TARGET_GENERICS) $(synth_files) -e toplevel; write_verilog $@" + $(YOSYS) -m $(GHDLSYNTH) -p "ghdl --std=08 --no-formal $(GHDL_IMAGE_GENERICS) $(synth_files) -e toplevel; write_verilog $@" # Need to investigate why yosys is hitting verilator warnings, and eventually turn on -Wall microwatt-verilator: microwatt.v verilator/microwatt-verilator.cpp verilator/uart-verilator.c - verilator -O3 -CFLAGS "-DCLK_FREQUENCY=$(CLK_FREQUENCY)" --assert --cc microwatt.v --exe verilator/microwatt-verilator.cpp verilator/uart-verilator.c -o $@ -Iuart16550 -Wno-fatal -Wno-CASEOVERLAP -Wno-UNOPTFLAT #--trace + verilator $(VERILATOR_FLAGS) -CFLAGS "$(VERILATOR_CFLAGS) -DCLK_FREQUENCY=$(CLK_FREQUENCY)" --assert --cc $< --exe verilator/microwatt-verilator.cpp verilator/uart-verilator.c -o $@ -Iuart16550 -Wno-fatal -Wno-CASEOVERLAP -Wno-UNOPTFLAT make -C obj_dir -f Vmicrowatt.mk @cp -f obj_dir/microwatt-verilator microwatt-verilator