X-Git-Url: https://git.libre-soc.org/?a=blobdiff_plain;f=README;h=1bfa21be22584cf1e0bd3c1c12fe8247a0ae1a45;hb=512ed2b3d60694998a4d905a9d7c130e257e9981;hp=6eff1b4efdc17c67678e26ab93294547b1d00b37;hpb=6a0f85dc423f0c98f483d85f2c4cd57b31270a8b;p=litex.git

diff --git a/README b/README
index 6eff1b4e..1bfa21be 100644
--- a/README
+++ b/README
@@ -2,30 +2,32 @@
                       / /  (_) /____ | |/_/
                      / /__/ / __/ -_)>  <
                     /____/_/\__/\__/_/|_|
+                         Migen inside
 
                 Build your hardware, easily!
-                Copyright 2015 Enjoy-Digital
-             (based on Migen/MiSoC technologies)
+             Copyright 2012-2018 Enjoy-Digital
 
 [> Intro
----------
-LiteX is a fork of Migen/MiSoC for our own needs at Enjoy-Digital. It provides
-a single python package and add some specific features to design our FPGA cores,
-build a SoC with or or load/flash it to the hardware.
+--------
+LiteX is an alternative to Migen/MiSoC maintained and used by Enjoy-Digital
+to build our cores, integrate them in complete SoC and load/flash them to
+the hardware and experiment new features.
 
-The structure of LiteX is kept close to Migen/MiSoC to enable collaboration
-between projects.
+The structure of LiteX is kept close to Migen/MiSoC to ease collaboration
+between projects and efforts are made to keep cores developed with LiteX
+compatible with Migen/MiSoC.
 
 [> License
------------
-LiteX is copyright (c) 2015 Enjoy-Digital.
-Since it is based on Migen/MiSoC, see gen/MIGEN_LICENSE and soc/MISOC_LICENSE or
-git history to get correct ownership of files.
+----------
+LiteX is Copyright (c) 2012-2017 Enjoy-Digital under BSD Lisense.
+Since it is based on Migen/MiSoC, please also refer to LICENSE file in gen/soc
+directory or git history to get correct copyrights.
 
 [> Sub-packages
------------
+---------------
 gen:
-  Provides tools and simple modules to generate HDL.
+  Provides specific or experimental modules to generate HDL that are not integrated
+  in Migen.
 
 build:
   Provides tools to build FPGA bitstreams (interface to vendor toolchains) and to
@@ -38,5 +40,41 @@ soc:
 boards:
   Provides platforms and targets for the supported boards.
 
+[> Quick start guide
+--------------------
+0. If cloned from Git without the --recursive option, get the submodules:
+  git submodule update --init
+
+1. Install Python 3.3+ and FPGA vendor's development tools and JTAG tools.
+
+2. Compile and install binutils. Take the latest version from GNU.
+  mkdir build && cd build
+  ../configure --target=lm32-elf
+  make
+  make install
+
+3. (Optional, only if you want to use a lm32 CPU in you SoC)
+  Compile and install GCC. Take gcc-core and gcc-g++ from GNU
+  (version 4.5 or >=4.9).
+  rm -rf libstdc++-v3
+  mkdir build && cd build
+  ../configure --target=lm32-elf --enable-languages="c,c++" --disable-libgcc \
+    --disable-libssp
+  make
+  make install
+
+4. Build the target of your board...:
+  Go to boards/targets and execute the target you want to build
+
+5. ... and/or install Verilator and test LiteX on your computer:
+  Download and install Verilator: http://www.veripool.org/
+  Install libevent-devel / json-c-devel packages
+  Go to boards/targets
+  ./sim.py
+
+6. Run a terminal program on the board's serial port at 115200 8-N-1.
+  You should get the BIOS prompt.
+
 [> Contact
+----------
 E-mail: florent [AT] enjoy-digital.fr
\ No newline at end of file