X-Git-Url: https://git.libre-soc.org/?a=blobdiff_plain;f=README;h=1bfa21be22584cf1e0bd3c1c12fe8247a0ae1a45;hb=512ed2b3d60694998a4d905a9d7c130e257e9981;hp=c310196d7e231e29d5c8572016cb2d9f265f1623;hpb=64d18796e0f8015c448d47d7c63362b7c4a39f4c;p=litex.git diff --git a/README b/README index c310196d..1bfa21be 100644 --- a/README +++ b/README @@ -1,125 +1,80 @@ - __ _ __ ____ - / / (_) /____ / __/______ ___ ___ - / /__/ / __/ -_)\ \/ __/ _ \/ _ \/ -_) - /____/_/\__/\__/___/\__/\___/ .__/\__/ - /_/ - Copyright 2012-2015 / EnjoyDigital - florent@enjoy-digital.fr + __ _ __ _ __ + / / (_) /____ | |/_/ + / /__/ / __/ -_)> < + /____/_/\__/\__/_/|_| + Migen inside - A small footprint and configurable embedded FPGA - logic analyzer core by EnjoyDigital + Build your hardware, easily! + Copyright 2012-2018 Enjoy-Digital [> Intro ---------- -LiteScope is small footprint and configurable embedded logic analyzer that you -can use in your FPGA and aims to provide a a free, portable and flexible -alternatve to vendor's solutions! - -LiteScope is part of LiteX libraries whose aims are to lower entry level of complex -FPGA IP cores by providing simple, elegant and efficient implementations of -components used in today's SoC such as Ethernet, SATA, PCIe, SDRAM Controller... - -The core uses simple and specific streaming buses and will provides in the future -adapters to use standardized AXI or Avalon-ST streaming buses. - -Since Python is used to describe the HDL, the core is highly and easily -configurable. - -LiteScope uses technologies developed in partnership with M-Labs Ltd: - - Migen enables generating HDL with Python in an efficient way. - - MiSoC provides the basic blocks to build a powerful and small footprint SoC. - -LiteScope can be used as a Migen/MiSoC library (by simply installing it -with the provided setup.py) or can be integrated with your standard design flow -by generating the verilog rtl that you will use as a standard core. - -LiteScope produces "vcd" files that can be read in your regular waveforms viewer. - -Since LiteScope also provides a UART <--> Wishbone brige so you only need 2 -external Rx/Tx pins to be ready to debug or control all your Wishbone peripherals! - -[> Features ------------ -- IO peek and poke with LiteScopeIO -- Logic analyser with LiteScopeLA: - - Various triggering modules: Term, Range, Edge (add yours! :) - - Run Length Encoder to "compress" data and increase recording depth - - Data storage in block rams - -[> Possibles improvements -------------------------- -- add standardized interfaces (AXI, Avalon-ST) -- add protocols analyzers -- add signals injection/generation -- add storage in DRAM -- add storage in HDD with LiteSATA core (to be released soon!) -- add Ethernet Wishbone bridge -- add PCIe Wishbone bridge with LitePCIe (to be released soon!) -- ... See below Support and Consulting :) - -If you want to support these features, please contact us at florent [AT] -enjoy-digital.fr. You can also contact our partner on the public mailing list -devel [AT] lists.m-labs.hk. - - -[> Getting started ------------------- -1. Install Python3 and your vendor's software - -2. Obtain Migen and install it: - git clone https://github.com/m-labs/migen - cd migen - python3 setup.py install - cd .. - -3. Obtain MiSoC: - git clone https://github.com/m-labs/misoc --recursive - XXX add setup.py to MiSoC for external use of misoclib? - -4. Obtain LiteScope - git clone https://github.com/enjoy-digital/litescope - -5. Build and load test design: - python3 make.py -s [platform] all - Supported platforms are the one altready supported by Mibuild: - de0nano, m1, mixxeo, kc705, zedboard... - -6. Test design: - go to ./test directory and run: - python3 test_io.py - python3 test_la.py - -[> Simulations: - XXX convert simulations - -[> Tests : - XXX convert tests +-------- +LiteX is an alternative to Migen/MiSoC maintained and used by Enjoy-Digital +to build our cores, integrate them in complete SoC and load/flash them to +the hardware and experiment new features. + +The structure of LiteX is kept close to Migen/MiSoC to ease collaboration +between projects and efforts are made to keep cores developed with LiteX +compatible with Migen/MiSoC. [> License ------------ -LiteScope is released under the very permissive two-clause BSD license. Under the -terms of this license, you are authorized to use LiteScope for closed-source -proprietary designs. -Even though we do not require you to do so, those things are awesome, so please -do them if possible: - - tell us that you are using LiteScope - - cite LiteScope in publications related to research it has helped - - send us feedback and suggestions for improvements - - send us bug reports when something goes wrong - - send us the modifications and improvements you have done to LiteScope. - -[> Support and Consulting --------------------------- -We love open-source hardware and like sharing our designs with others. - -LiteScope is developed and maintained by EnjoyDigital. - -If you would like to know more about LiteScope or if you are already a happy user -and would like to extend it for your needs, EnjoyDigital can provide standard -commercial support as well as consulting services. - -So feel free to contact us, we'd love to work with you! (and eventually shorten -the list of the possible improvements :) +---------- +LiteX is Copyright (c) 2012-2017 Enjoy-Digital under BSD Lisense. +Since it is based on Migen/MiSoC, please also refer to LICENSE file in gen/soc +directory or git history to get correct copyrights. + +[> Sub-packages +--------------- +gen: + Provides specific or experimental modules to generate HDL that are not integrated + in Migen. + +build: + Provides tools to build FPGA bitstreams (interface to vendor toolchains) and to + simulate HDL code or full SoCs. + +soc: + Provides definitions/modules to build cores (bus, bank, flow), cores and tools + to build a SoC from such cores. + +boards: + Provides platforms and targets for the supported boards. + +[> Quick start guide +-------------------- +0. If cloned from Git without the --recursive option, get the submodules: + git submodule update --init + +1. Install Python 3.3+ and FPGA vendor's development tools and JTAG tools. + +2. Compile and install binutils. Take the latest version from GNU. + mkdir build && cd build + ../configure --target=lm32-elf + make + make install + +3. (Optional, only if you want to use a lm32 CPU in you SoC) + Compile and install GCC. Take gcc-core and gcc-g++ from GNU + (version 4.5 or >=4.9). + rm -rf libstdc++-v3 + mkdir build && cd build + ../configure --target=lm32-elf --enable-languages="c,c++" --disable-libgcc \ + --disable-libssp + make + make install + +4. Build the target of your board...: + Go to boards/targets and execute the target you want to build + +5. ... and/or install Verilator and test LiteX on your computer: + Download and install Verilator: http://www.veripool.org/ + Install libevent-devel / json-c-devel packages + Go to boards/targets + ./sim.py + +6. Run a terminal program on the board's serial port at 115200 8-N-1. + You should get the BIOS prompt. [> Contact +---------- E-mail: florent [AT] enjoy-digital.fr \ No newline at end of file