X-Git-Url: https://git.libre-soc.org/?a=blobdiff_plain;f=README;h=216f4a047562f16540d0f7c39a915176971a7221;hb=a5416fa86424880722b9191991ce2f4bcd1fd7eb;hp=8b93ce0bc93ffd551e825ef79bce033c87116b1e;hpb=4a59b631514c3898132e01c29df175f592b9ef98;p=litex.git diff --git a/README b/README index 8b93ce0b..216f4a04 100644 --- a/README +++ b/README @@ -1,21 +1,142 @@ -[> migScope ------------- + __ _ __ ____ + / / (_) /____ / __/______ ___ ___ + / /__/ / __/ -_)\ \/ __/ _ \/ _ \/ -_) + /____/_/\__/\__/___/\__/\___/ .__/\__/ + /_/ + Copyright 2012-2015 / EnjoyDigital + florent@enjoy-digital.fr -This is a small Logic Analyser to be embedded in a Fpga design to debug internal -or external signals. + A small footprint and configurable embedded FPGA + logic analyzer core developed by EnjoyDigital -[> Status: -Early development phase +[> Doc +--------- +HTML : www.enjoy-digital.fr/litex/litescope/ +PDF : www.enjoy-digital.fr/litex/litescope.pdf -Simulation: --tb_spi2Csr : Test Spi <--> Csr Bridge : [Ok] --tb_TriggerCsr : Test Trigger with Csr : [Ok] --tb_RecorderCsr : Test Recorder with Csr : [Ok] --tb_MigScope : Global Test with Csr : [Ok] +[> Intro +--------- +LiteScope is small footprint and configurable embedded logic analyzer that you +can use in your FPGA and aims to provide a a free, portable and flexible +alternatve to vendor's solutions! -Example Design: --de0_nano : Generate Signals in FPGA and probe them with migScope : [Wip] +LiteScope is part of LiteX libraries whose aims are to lower entry level of complex +FPGA IP cores by providing simple, elegant and efficient implementations of +components used in today's SoC such as Ethernet, SATA, PCIe, SDRAM Controller... +The core uses simple and specific streaming buses and will provides in the future +adapters to use standardized AXI or Avalon-ST streaming buses. + +Since Python is used to describe the HDL, the core is highly and easily +configurable. + +LiteScope uses technologies developed in partnership with M-Labs Ltd: + - Migen enables generating HDL with Python in an efficient way. + - MiSoC provides the basic blocks to build a powerful and small footprint SoC. + +LiteScope can be used as a Migen/MiSoC library (by simply installing it +with the provided setup.py) or can be integrated with your standard design flow +by generating the verilog rtl that you will use as a standard core. + +LiteScope produces "vcd" files that can be read in your regular waveforms viewer. + +Since LiteScope also provides a UART <--> Wishbone brige so you only need 2 +external Rx/Tx pins to be ready to debug or control all your Wishbone peripherals! + +[> Features +----------- +- IO peek and poke with LiteScopeIO +- Logic analyser with LiteScopeLA: + - Various triggering modules: Term, Range, Edge (add yours! :) + - Run Length Encoder to "compress" data and increase recording depth + - Subsampling + - Storage qualifier + - Data storage in block rams +- Bridges: + - UART2Wishbone + - Ethernet2Wishbone ("Etherbone") + +[> Possible improvements +------------------------- +- add standardized interfaces (AXI, Avalon-ST) +- add protocols analyzers +- add signals injection/generation +- add storage in DRAM +- add storage in HDD with LiteSATA core (to be released soon!) +- add PCIe Wishbone bridge with LitePCIe (to be released soon!) +- ... See below Support and consulting :) + +If you want to support these features, please contact us at florent [AT] +enjoy-digital.fr. You can also contact our partner on the public mailing list +devel [AT] lists.m-labs.hk. + + +[> Getting started +------------------ +1. Install Python3 and your vendor's software + +2. Obtain Migen and install it: + git clone https://github.com/m-labs/migen + cd migen + python3 setup.py install + cd .. + +3. Obtain MiSoC and install it: + git clone https://github.com/m-labs/misoc --recursive + cd misoc + python3 setup.py install + cd .. + +Note: in case you have issues with Migen/MiSoC, please retry +with our forks at: + https://github.com/enjoy-digital/misoc + https://github.com/enjoy-digital/migen +until new features are merged. + +4. Obtain LiteScope and install it: + git clone https://github.com/enjoy-digital/litescope + +5. Build and load test design: + python3 make.py -s [platform] all + Supported platforms are the one altready supported by Mibuild: + de0nano, m1, mixxeo, kc705, zedboard... + +6. Test design: + go to ./test directory and run: + python3 test_io.py + python3 test_la.py + +[> Simulations: + XXX convert simulations + +[> Tests : + XXX convert tests + +[> License +----------- +LiteScope is released under the very permissive two-clause BSD license. Under the +terms of this license, you are authorized to use LiteScope for closed-source +proprietary designs. +Even though we do not require you to do so, those things are awesome, so please +do them if possible: + - tell us that you are using LiteScope + - cite LiteScope in publications related to research it has helped + - send us feedback and suggestions for improvements + - send us bug reports when something goes wrong + - send us the modifications and improvements you have done to LiteScope. + +[> Support and consulting +-------------------------- +We love open-source hardware and like sharing our designs with others. + +LiteScope is developed and maintained by EnjoyDigital. + +If you would like to know more about LiteScope or if you are already a happy user +and would like to extend it for your needs, EnjoyDigital can provide standard +commercial support as well as consulting services. + +So feel free to contact us, we'd love to work with you! (and eventually shorten +the list of the possible improvements :) [> Contact -E-mail: florent@enjoy-digital.fr +E-mail: florent [AT] enjoy-digital.fr \ No newline at end of file