X-Git-Url: https://git.libre-soc.org/?a=blobdiff_plain;f=README.md;h=cc5c806fb023dd6a96f3af3b929a06b4a21cf4f5;hb=493b5e03e7ce9496980c9235bb2979bd259995a6;hp=770c624591bd045d582f12ed5ca2819c79bfdddc;hpb=369dcb4e824ea18957b4ad989f50f757674799c3;p=yosys.git

diff --git a/README.md b/README.md
index 770c62459..cc5c806fb 100644
--- a/README.md
+++ b/README.md
@@ -1,7 +1,7 @@
 ```
 yosys -- Yosys Open SYnthesis Suite
 
-Copyright (C) 2012 - 2020  Claire Wolf <claire@symbioticeda.com>
+Copyright (C) 2012 - 2020  Claire Xenia Wolf <claire@yosyshq.com>
 
 Permission to use, copy, modify, and/or distribute this software for any
 purpose with or without fee is hereby granted, provided that the above
@@ -38,13 +38,13 @@ Web Site and Other Resources
 ============================
 
 More information and documentation can be found on the Yosys web site:
-- http://www.clifford.at/yosys/
+- https://yosyshq.net/yosys/
 
 The "Documentation" page on the web site contains links to more resources,
 including a manual that even describes some of the Yosys internals:
-- http://www.clifford.at/yosys/documentation.html
+- https://yosyshq.net/yosys/documentation.html
 
-The file `CodingReadme` in this directory contains additional information
+The directory `guidelines` contains additional information
 for people interested in using the Yosys C++ APIs.
 
 Users interested in formal verification might want to use the formal verification
@@ -92,7 +92,7 @@ For Cygwin use the following command to install all prerequisites, or select the
 
 There are also pre-compiled Yosys binary packages for Ubuntu and Win32 as well
 as a source distribution for Visual Studio. Visit the Yosys download page for
-more information: http://www.clifford.at/yosys/download.html
+more information: https://yosyshq.net/yosys/download.html
 
 To configure the build system to use a specific compiler, use one of
 
@@ -309,7 +309,9 @@ Verilog Attributes and non-standard features
   that have ports with a width that depends on a parameter.
 
 - The ``hdlname`` attribute is used by some passes to document the original
-  (HDL) name of a module when renaming a module.
+  (HDL) name of a module when renaming a module. It should contain a single
+  name, or, when describing a hierarchical name in a flattened design, multiple
+  names separated by a single space character.
 
 - The ``keep`` attribute on cells and wires is used to mark objects that should
   never be removed by the optimizer. This is used for example for cells that
@@ -487,6 +489,11 @@ Verilog Attributes and non-standard features
   for use in blackboxes and whiteboxes. Use ``read_verilog -specify`` to
   enable this functionality. (By default these blocks are ignored.)
 
+- The ``reprocess_after`` internal attribute is used by the Verilog frontend to
+  mark cells with bindings which might depend on the specified instantiated
+  module. Modules with such cells will be reprocessed during the ``hierarchy``
+  pass once the referenced module definition(s) become available.
+
 
 Non-standard or SystemVerilog features for formal verification
 ==============================================================
@@ -566,7 +573,7 @@ Building the documentation
 ==========================
 
 Note that there is no need to build the manual if you just want to read it.
-Simply download the PDF from http://www.clifford.at/yosys/documentation.html
+Simply download the PDF from https://yosyshq.net/yosys/documentation.html
 instead.
 
 On Ubuntu, texlive needs these packages to be able to build the manual: