X-Git-Url: https://git.libre-soc.org/?a=blobdiff_plain;f=README.txt;fp=README.txt;h=ca3ba1ae43b5decb9c11c228300ca4d564d2b33c;hb=25d14007b011dd77a3b88878f124127fef29640e;hp=0000000000000000000000000000000000000000;hpb=0434ba1d907755fe3057f1d2f2f1d487b02279b9;p=rv32.git

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+# Limitations
+
+* there is no << or >> operator, only <<< and >>> (arithmetic shift)
+  _Operator("<<", [lhs, rhs]) will generate verilog however simulation
+  will fail, and value_bits_sign will not correctly recognise it
+* it is not possible to declare parameters
+* an input of [31:2] is not possible, only a parameter of [N:0]
+* tasks are not supported.
+* Clock Domains: https://gist.github.com/cr1901/5de5b276fca539b66fe7f4493a5bfe7d