X-Git-Url: https://git.libre-soc.org/?a=blobdiff_plain;f=RELEASE_NOTES;h=f10ffddae62104e8dcc05242add81c3b8105a6b3;hb=4e1adf85f77edf761466af3568576d3f9134a14c;hp=103bc0b7a868eb6fc3ae8a51ad03532137830ed4;hpb=bf02aed7b7466ba7a5fe111b77949462c8884f95;p=gem5.git

diff --git a/RELEASE_NOTES b/RELEASE_NOTES
index 103bc0b7a..f10ffddae 100644
--- a/RELEASE_NOTES
+++ b/RELEASE_NOTES
@@ -1,22 +1,51 @@
+October 6, 2008: m5_2.0_beta6
+--------------------
+New Features
+1. Support for gcc 4.3
+2. Core m5 code in libm5 for integration with other simulators
+3. Preliminary support for X86 SE mode
+4. Additional system calls emulated
+5. m5term updated to work on OS X
+6. Ability to disable listen sockets
+7. Event queue performance improvements and rewrite
+8. Better errors for unconnected memory ports
+
+Bug fixes
+1. ALPHA_SE O3 perlbmk benchmark
+2. Translation bug where O3 could fetch from uncachable memory
+3. Many minor bugs
+
 Outstanding issues for 2.0 release:
 --------------------
-1. Fix O3 CPU bug in SE 40.perlbmk fails
-2. Fix O3 processing nacks/coherence messages
-3. Better statistics for the caches.
-4. FS mode doesn't work under Cygwin
-5. memtest regression crashes under Cygwin
-6. Make repository public
-7. Testing
-8. Validation
-9. Testing 
-
-Nov XX, 2007: m5_2.0_beta4
+1. Statistics cleanup
+2. Improve regression system
+3. Testing
+4. Validation
+
+March 1, 2008: m5_2.0_beta5
+--------------------
+New Features
+1. Rick Strong's Simpoints config changes
+2. Support for FSU ARM port
+3. EXTRAS= option allow architectures to be specified
+
+Bug fixes
+1. Bus timing more realistic
+2. Cache writeback, LL/SC fixes
+3. Minor IGbE NIC fixes
+4. O3 op latency fix
+5. SPARC TLB demap fixes
+6. SPARC SE memory layout fixes
+7. Variety of MIPS fixes
+
+Nov 4, 2007: m5_2.0_beta4
 --------------------
 New Features
-1. New cache 
-2. Ability to include compiled code with EXTRAS=
-3. Python creation of params structures for initialization
-4. Ability to remotely debug in SE 
+1. New cache model
+2. Use of a I/O cache between devices and memory 
+3. Ability to include compiled code with EXTRAS=
+4. Python creation of params structures for initialization
+5. Ability to remotely debug in SE 
 
 Bug fixes:
 1. Fix SE serialization
@@ -26,6 +55,21 @@ Bug fixes:
 5. Draining code for checkpointing
 6. Various performance improvements
 
+Possible Incompatibilities:
+1. Real TLBs are now used in SE mode. This is more accurate however it could
+   cause some problems if you've modified the way page handling is done in
+   SE mode.
+2. There have been many changes to the way the SCons files work. SimObjects,
+   sources files, and trace flags are all specified in the SConscript files.
+   To see how to add your sources take a look at one of them.
+3. Python is now used to created the parameter structs that were created
+   manually before. The parameters listed in a py file are turned into 
+   a header file with the same name (e.g. BadDevice.py -> BadDevice.hh). 
+   With this change the structs can be populated automatically and the 
+   ugly macros to define and create SimObjects at the bottem of source
+   files are gone. The parameter structs also automatically inherit 
+   parameters from their parents. 
+
 May 16, 2007: m5_2.0_beta3
 --------------------
 New Features