X-Git-Url: https://git.libre-soc.org/?a=blobdiff_plain;f=about_us.mdwn;h=3c8345dffa2d203b4ecfd4488332900c276c4e89;hb=73e56fdf2219ac2aa749b356c778b83994671574;hp=c74ced180bbb51f458ca3487a68dc27ced42a840;hpb=d492196776068ee41b6566667c536d9f771a41e1;p=libreriscv.git

diff --git a/about_us.mdwn b/about_us.mdwn
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--- a/about_us.mdwn
+++ b/about_us.mdwn
@@ -215,10 +215,11 @@ Alain's website: <http://phcomp.co.uk>
 * Experience: FPGA/ASIC system validation, instrument automation using VISA, PCB design (KiCAD, Altium)
 * Other interests: Lingua Latina, Philosophy, History
 * Availability: Full-time
+* IRC: octavius
 
 ## [[Manikandan Nagarajan|Manik]]
 
-* Languages: Verilog HDL, C, Python & TCL
+* Languages: Verilog HDL, VHDL, C, Python & TCL
 * Experience : Domain Specific Architecture Design and Implementation, IP Core Development, System on Chip, FPGA System Design, Chip Tapeout, Crypto Chip Design, Authentication Protocol Design. 
 * LinkedIn Profile: [[https://www.linkedin.com/in/manikandan-nagarajan-2156171a0/]]
 * Availability: 8~10hrs/week