X-Git-Url: https://git.libre-soc.org/?a=blobdiff_plain;f=about_us.mdwn;h=fbd1d24bd7168d6fce9f86b88205501fbf00d37a;hb=29e70a8394521994e82f5635822f15b711b150ad;hp=d36713bf42aa49273a273e379735e5a0dcf9ffb7;hpb=b2c94f89c0087d88f2af518aa4d59b87cb7af5a1;p=libreriscv.git

diff --git a/about_us.mdwn b/about_us.mdwn
index d36713bf4..fbd1d24bd 100644
--- a/about_us.mdwn
+++ b/about_us.mdwn
@@ -137,11 +137,22 @@ Alain's website: <http://phcomp.co.uk>
 * Availability:  10+hrs/week, more is negotiable
 * Timezone:  UTC-07:00 (DST UTC-06:00, 2nd Sun of Mar-1st Sun of Nov)
 
+## [[Mikolaj Wielgus|mikolajw]]
+
+* Interests: Libre software and hardware, analog circuits, RF and microwave circuits, nonlinear systems, oscillators
+* Hardware Experience: PCB schematic and layout design, very small amount of IC design
+* Software Experience: Data acquisition and processing (LXI, SCPI), GUI development (wxWidgets), Microcontroller programming (AVR, STM32), video game development (Love2D, SDL)
+* Languages: Verilog, Asm (AVR), C, C++, C#, D, Python, Octave, Lua, Java, or any other language involving a similar set of abstractions
+* GitLab: https://gitlab.com/mwielgus
+* Most of my skills are self-taught by making small amateur projects. I have only little industry experience.
+* Availability: ~6 hrs/week
+* Timezone: UTC+01:00
+
 ## Object Automation
 
 ### [[oa/madan]]
 
-* Experience: Programming in Python and Knowledge of ML algorithms and NLP
+* Interests: Programming in Python and Knowledge of ML algorithms and NLP
 * Availability: 5 hours per week
 * Statistician
 
@@ -154,7 +165,9 @@ Alain's website: <http://phcomp.co.uk>
 
 ### [[oa/adithya]]
 
-TODO, Adithya
+* Interests:Digital System Design,PCB layout, Programming, Machine Learning, IoT
+* Programming Languages: Verilog, C, C++, Java, Python3, Julia
+* Availability: ~10hrs per week
 
 ### [[oa/Niranjan]]
 
@@ -168,12 +181,6 @@ TODO, Adithya
 * Programming Languages: C, Python, Java, VHDL
 * Availability: ~8-10 hours/week
 
-### [[oa/Akshara S]]
-
-* Interests: Embedded systems, Analog Electronics
-* Programming Languages: C, Python, Verilog
-* Availability: ~ 3-4 hours/week
-
 ### [[oa/Sukhanshu D]]
 
 * Experience: SOC Verification Intern, Digital Design
@@ -185,11 +192,7 @@ TODO, Adithya
 * Interests: Digital Design, Verification, IC Fabrication
 * Programming Languages: Verilog, System Verilog, UVM
 * Availability: ~ 6-8 hours/week
-* Experience: SoC Verification Intern, Research Intern at KIST
-
-### [[oa/sparsha]]
-
-TODO
+* Experience: SoC Verification Intern, Research Intern at KIS
 
 ## 3mdeb
 
@@ -199,3 +202,23 @@ TODO
 * Languages: C, C++, Python
 * FW experience: system programming
 * Availability: depends on a week (0..10+hrs/week)
+
+## [[Kyle Lehman|klehman]]
+
+* Languages: C/C++, Java, Python, SQL, assembly
+* Interests: Language design, microacrhitecture, OS design, emulation, 3D computation 
+* Other interests: Nearly anything that floats, flies, or has an engine with wheels
+
+## [[Andrey Miroshnikov|andreym]]
+* Languages: C, Python, Verilog
+* Interests: Analogue/digital electronics, RF, mobile comms, compilers, FPGAs, discrete mathematics, microarchitecture, Unix OSs, PCB design
+* Experience: FPGA/ASIC system validation, instrument automation using VISA, PCB design (KiCAD, Altium)
+* Other interests: Lingua Latina, Philosophy, History
+* Availability: Full-time
+
+## [[Manikandan Nagarajan|Manik]]
+
+* Languages: Verilog HDL, VHDL, C, Python & TCL
+* Experience : Domain Specific Architecture Design and Implementation, IP Core Development, System on Chip, FPGA System Design, Chip Tapeout, Crypto Chip Design, Authentication Protocol Design. 
+* LinkedIn Profile: [[https://www.linkedin.com/in/manikandan-nagarajan-2156171a0/]]
+* Availability: 8~10hrs/week