X-Git-Url: https://git.libre-soc.org/?a=blobdiff_plain;f=arch%2Fisa_parser.py;h=2e3c0df3540e68920fd1a3a3c5bb5c605486db9d;hb=74fd8b1ad106c98e08bc433a6cc63a3c6cf564df;hp=a4b588197e1f7c30eb7a8cd1e0b5d5e4f4c2f120;hpb=92638f9a657207ad6f0bc301597d9e1a3c1158e2;p=gem5.git

diff --git a/arch/isa_parser.py b/arch/isa_parser.py
old mode 100644
new mode 100755
index a4b588197..2e3c0df35
--- a/arch/isa_parser.py
+++ b/arch/isa_parser.py
@@ -246,6 +246,10 @@ def p_specification(t):
  * The Regents of The University of Michigan
  * All Rights Reserved
  *
+ * This code is part of the M5 simulator, developed by Nathan Binkert,
+ * Erik Hallnor, Steve Raasch, and Steve Reinhardt, with contributions
+ * from Ron Dreslinski, Dave Greene, and Lisa Hsu.
+ *
  * Permission is granted to use, copy, create derivative works and
  * redistribute this software and such derivative works for any
  * purpose, so long as the copyright notice above, this grant of
@@ -275,7 +279,7 @@ def p_specification(t):
  *    RCS %(local_rcs_id)s
  */
 
-#include "bitfield.hh"	// required for bitfield support
+#include "base/bitfield.hh"	// required for bitfield support
 
 
 /////////////////////////////////////