X-Git-Url: https://git.libre-soc.org/?a=blobdiff_plain;f=base%2Ftraceflags.py;h=3f5056ed8a8acfac22407e69af5941fdce54d924;hb=62fa781fee9ae93432e81902d73a35a83dbde642;hp=69f4e7ab851ec075b46a4d42a3117bbda8340d7f;hpb=1c1acf553a90dc1eab253d65d98dc6be8f7d066f;p=gem5.git diff --git a/base/traceflags.py b/base/traceflags.py index 69f4e7ab8..3f5056ed8 100644 --- a/base/traceflags.py +++ b/base/traceflags.py @@ -30,8 +30,15 @@ # This file generates the header and source files for the flags # that control the tracing facility. # -hhfilename="traceflags.hh" -ccfilename="traceflags.cc" + +import sys + +if len(sys.argv) != 2: + print "%s: Need argument (basename of cc/hh files)" % sys.argv[0] + sys.exit(1) + +hhfilename = sys.argv[1] + '.hh' +ccfilename = sys.argv[1] + '.cc' # # The list of trace flags that can be used to condition DPRINTFs etc. @@ -57,15 +64,16 @@ baseFlags = [ 'Mbox', 'PCIA', 'PCIDEV', + 'PciConfigAll', 'ISP', 'BADADDR', 'Console', 'ConsolePoll', 'ConsoleVerbose', - 'TlaserUart', 'AlphaConsole', 'Flow', 'Interrupt', + 'Fault', 'Cycle', 'Loader', 'MMU', @@ -73,6 +81,10 @@ baseFlags = [ 'EthernetPIO', 'EthernetDMA', 'EthernetData', + 'EthernetDesc', + 'EthernetIntr', + 'EthernetSM', + 'EthernetCksum', 'GDBMisc', 'GDBAcc', 'GDBRead', @@ -98,13 +110,37 @@ baseFlags = [ 'IICMore', 'MSHR', 'Chains', - 'Dispatch', + 'Pipeline', 'Stats', 'StatEvents', 'Context', 'Config', 'Sampler', - 'WriteBarrier' + 'WriteBarrier', + 'IdeCtrl', + 'IdeDisk', + 'Tsunami', + 'Uart', + 'Split', + 'SQL', + 'Thread', + 'Fetch', + 'Decode', + 'Rename', + 'IEW', + 'Commit', + 'IQ', + 'ROB', + 'FreeList', + 'RenameMap', + 'LDSTQ', + 'StoreSet', + 'MemDepUnit', + 'DynInst', + 'FullCPU', + 'CommitRate', + 'OoOCPU', + 'HWPrefetch' ] # @@ -119,7 +155,10 @@ compoundFlagMap = { 'GDBAll' : [ 'GDBMisc', 'GDBAcc', 'GDBRead', 'GDBWrite', 'GDBSend', 'GDBRecv', 'GDBExtra' ], 'ScsiAll' : [ 'ScsiDisk', 'ScsiCtrl', 'ScsiNone' ], 'DiskImageAll' : [ 'DiskImage', 'DiskImageRead', 'DiskImageWrite' ], - 'EthernetAll' : [ 'Ethernet', 'EthernetPIO', 'EthernetDMA', 'EthernetData' ] + 'EthernetAll' : [ 'Ethernet', 'EthernetPIO', 'EthernetDMA', 'EthernetData' , 'EthernetDesc', 'EthernetIntr', 'EthernetSM', 'EthernetCksum' ], + 'EthernetNoData' : [ 'Ethernet', 'EthernetPIO', 'EthernetDesc', 'EthernetIntr', 'EthernetSM', 'EthernetCksum' ], + 'IdeAll' : [ 'IdeCtrl', 'IdeDisk' ], + 'FullCPUAll' : [ 'Fetch', 'Decode', 'Rename', 'IEW', 'Commit', 'IQ', 'ROB', 'FreeList', 'RenameMap', 'LDSTQ', 'StoreSet', 'MemDepUnit', 'DynInst', 'FullCPU'] } #############################################################