X-Git-Url: https://git.libre-soc.org/?a=blobdiff_plain;f=benchmarks%2Fcommon%2Fcrt.S;h=b273900e880957ee7a82f9790c369cd22fc13ca3;hb=d9d10ada1e5ade369128c4fd12fcfe1693288eed;hp=ae8706bfa831752588cd77fd031d22f77673b881;hpb=b374fd10b2b36124bb6813211a7ec690e1fa8350;p=riscv-tests.git

diff --git a/benchmarks/common/crt.S b/benchmarks/common/crt.S
index ae8706b..b273900 100644
--- a/benchmarks/common/crt.S
+++ b/benchmarks/common/crt.S
@@ -1,5 +1,13 @@
 #include "encoding.h"
 
+#ifdef __riscv64
+# define LREG ld
+# define SREG sd
+#else
+# define LREG lw
+# define SREG sw
+#endif
+
   .data
   .globl _heapend
   .globl environ
@@ -48,6 +56,7 @@ _start:
   li a0, SR_U64 | SR_S64
   csrs status, a0
 #endif
+  csrc status, SR_PS
 
   # enable fp and accelerator
   li a0, SR_EF | SR_EA
@@ -93,48 +102,130 @@ _start:
   fmv.s.x f31,x0
 1:
 
-  lui a0, %hi(trap_entry)    
-  add a0, a0, %lo(trap_entry)
-  csrw evec, a0
+  la t0, trap_entry
+  csrw evec, t0
+
+  la  tp, _end + 63
+  and tp, tp, -64
 
-  lui a0, %hi(main)    
-  add a0, a0, %lo(main)
-  csrw epc, a0
+  # get core id and number of cores
+  csrr a0, hartid
+  lw a1, 4(zero)
 
-  # only allow core 0 to proceed
-1:csrr a0, hartid
-  bnez a0, 1b
+  # give each core 128KB of stack + TLS
+#define STKSHIFT 17
+  sll a2, a0, STKSHIFT
+  add tp, tp, a2
+  add sp, a0, 1
+  sll sp, sp, STKSHIFT
+  add sp, sp, tp
 
-  la  sp,stacktop
-  
-  # jmp to main as a user program
-  sret 
-1:b 1b
+  lui t0, %tprel_hi(tls_start)
+  add t0, t0, %tprel_lo(tls_start)
+  sub tp, tp, t0
+
+  la t0, _init
+  csrw epc, t0
+  sret
+
+trap_entry:
+  csrw sup0, sp
+  csrw sup1, t0
+  csrr t0, status
+  andi t0, t0, SR_PS
+  bnez t0, 1f
+  la sp, kstacktop
+1:
+  addi sp, sp, -272
+  csrr t0, sup1
 
+  SREG x1, 8(sp)
+  SREG x2, 16(sp)
+  SREG x3, 24(sp)
+  SREG x4, 32(sp)
+  SREG x5, 40(sp)
+  SREG x6, 48(sp)
+  SREG x7, 56(sp)
+  SREG x8, 64(sp)
+  SREG x9, 72(sp)
+  SREG x10, 80(sp)
+  SREG x11, 88(sp)
+  SREG x12, 96(sp)
+  SREG x13, 104(sp)
+  SREG x14, 112(sp)
+  SREG x15, 120(sp)
+  SREG x16, 128(sp)
+  SREG x17, 136(sp)
+  SREG x18, 144(sp)
+  SREG x19, 152(sp)
+  SREG x20, 160(sp)
+  SREG x21, 168(sp)
+  SREG x22, 176(sp)
+  SREG x23, 184(sp)
+  SREG x24, 192(sp)
+  SREG x25, 200(sp)
+  SREG x26, 208(sp)
+  SREG x27, 216(sp)
+  SREG x28, 224(sp)
+  SREG x29, 232(sp)
+  SREG x30, 240(sp)
+  SREG x31, 248(sp)
+
+  csrr t0, sup0
+  csrr t1, status
+  SREG t0, 256(sp)
+  SREG t1, 264(sp)
+
+  csrr a0, cause
+  csrr a1, epc
+  mv a2, sp
+  jal handle_trap
+  csrw epc, v0
+
+  LREG t0, 256(sp)
+  LREG t1, 264(sp)
+  csrw sup0, t0
+  csrw status, t1
+
+  LREG x1, 8(sp)
+  LREG x2, 16(sp)
+  LREG x3, 24(sp)
+  LREG x4, 32(sp)
+  LREG x5, 40(sp)
+  LREG x6, 48(sp)
+  LREG x7, 56(sp)
+  LREG x8, 64(sp)
+  LREG x9, 72(sp)
+  LREG x10, 80(sp)
+  LREG x11, 88(sp)
+  LREG x12, 96(sp)
+  LREG x13, 104(sp)
+  LREG x14, 112(sp)
+  LREG x15, 120(sp)
+  LREG x16, 128(sp)
+  LREG x17, 136(sp)
+  LREG x18, 144(sp)
+  LREG x19, 152(sp)
+  LREG x20, 160(sp)
+  LREG x21, 168(sp)
+  LREG x22, 176(sp)
+  LREG x23, 184(sp)
+  LREG x24, 192(sp)
+  LREG x25, 200(sp)
+  LREG x26, 208(sp)
+  LREG x27, 216(sp)
+  LREG x28, 224(sp)
+  LREG x29, 232(sp)
+  LREG x30, 240(sp)
+  LREG x31, 248(sp)
+
+  csrr sp, sup0
+  sret
+
+.bss
 .align 4
-.globl trap_entry
-trap_entry:                # only check for SYS_exit, otherwise crash out
-  li a3, 1337              # magic "bad things" happened error code
-  csrr a1, cause
-  li a2, 6                 # syscall exception number
-  bne a1, a2, exit_error
-handle_syscall:
-  li a1, 93                # SYS_exit number
-  bne v0, a1, exit_error
-  li a1, 1                 # successful exit code
-  move a3, a0
-  bne a3, a1, exit_error
-  csrw tohost, a1          # exit successfully (tohost == 1)
-1:b 1b
-exit_error:
-  sll a3, a3, 1
-  or  a3, a3, 1
-  csrw tohost, a3
-1:b 1b
-
-  .bss
-  .globl stacktop
-
-  .align 4
-  .skip 131072
-stacktop:
+.skip 4096
+kstacktop:
+
+.section .tbss
+tls_start: