X-Git-Url: https://git.libre-soc.org/?a=blobdiff_plain;f=cole.mdwn;h=2fe174ee3fd9fa4e4d30d50437e9456706189f0b;hb=d1c4c5d08320411b1c613e3160d4bcb4906d6224;hp=1cbb26f8cec1346456d7e82ceac2c0cc169c636f;hpb=4ed62259562d04fcd1feabf209913a109f9b683e;p=libreriscv.git

diff --git a/cole.mdwn b/cole.mdwn
index 1cbb26f8c..2fe174ee3 100644
--- a/cole.mdwn
+++ b/cole.mdwn
@@ -1,6 +1,6 @@
 # Cole Poirier
 
-Apprentice and assistant Project coordinator for Libre-SOC
+Former Apprentice at Libre-SOC
 
 * [Bugtracker assignments](https://bugs.libre-soc.org/buglist.cgi?email1=colepoirier%40gmail.com&emailassigned_to1=1&emailcc1=1&emailtype1=substring&resolution=---)
 
@@ -10,16 +10,24 @@ move things along from one stage to the next
 
 ## Currently working on
 
+- Reach out to lu_zero of Gentoo about SV POWER binutils
+- <https://bugs.libre-soc.org/show_bug.cgi?id=486> Script and document the setup and installation of microwatt dependency on the wiki-HDL_workflow page 
+- <https://bugs.libre-soc.org/show_bug.cgi?id=448> MUL tests
+  - shared with lkcl
+- <https://bugs.libre-soc.org/show_bug.cgi?id=484> Write VHDL to expose CR and XER from Microwatt so single-stepping is possible
+  - shared with lkcl
+- <https://bugs.libre-soc.org/show_bug.cgi?id=485> Create I-Cache from microwatt icache.vhdl
+  - shared with lkcl
+- <https://bugs.libre-soc.org/show_bug.cgi?id=469> Create D-cache from microwatt dcache.vhdl
+  - shared with lkcl
+- <https://bugs.libre-soc.org/show_bug.cgi?id=450> Create MMU from microwatt mmu.vhdl
+  - shared with lkcl
 - <https://bugs.libre-soc.org/show_bug.cgi?id=375> Recruiting more engineers to the project
 - <https://bugs.libre-soc.org/show_bug.cgi?id=380> First round of recruitment attempts
 - <https://bugs.libre-soc.org/show_bug.cgi?id=379> Create wiki page for recruitment emails to point to
-
 - <https://bugs.libre-soc.org/show_bug.cgi?id=388> bpermd tutorial 
-
 - <https://bugs.libre-soc.org/show_bug.cgi?id=389> Create bug report for each diagram to be converted to SVG 
-
 - <https://bugs.libre-soc.org/show_bug.cgi?id=394> Contact 'BlackParrot' RV64GC Multicore SoC devs
-
 - <https://bugs.libre-soc.org/show_bug.cgi?id=442> Convert comp_unit_req_rel diagram to SVG
 
 ## List of things that need more fleshed out bug reports:
@@ -27,24 +35,54 @@ move things along from one stage to the next
 - Scoreboard documentation
   - <http://lists.libre-riscv.org/pipermail/libre-riscv-dev/2020-June/008287.html>
 
+
 - LDST documentation
   - <http://lists.libre-riscv.org/pipermail/libre-riscv-dev/2020-June/008287.html>
 
-## Completed but not yet submitted
-
-- <https://bugs.libre-soc.org/show_bug.cgi?id=401> Convert 180nm Test ASIC Mem Layout diagram to SVG 
 
-- Coriolis2 documentation and setup scripts
-  - <https://bugs.libre-soc.org/show_bug.cgi?id=291>
-  - <https://bugs.libre-soc.org/show_bug.cgi?id=178>
-  - <https://bugs.libre-soc.org/show_bug.cgi?id=320>
-  - <https://bugs.libre-soc.org/show_bug.cgi?id=404>
-  - <https://bugs.libre-soc.org/show_bug.cgi?id=138> 
+## Completed but not yet submitted
 
 ## Submitted for NLNet RFP
 
 submitted but not confirmed paid:
 
-### Project 2019-02-012 Date {TEMPLATE INSERT DATE}
-
 ## Paid
+
+### MOU coriolis2 2019-10-029, received payment on 2021-MAY-5
+
+- <https://bugs.libre-soc.org/show_bug.cgi?id=502> determine SRAM block size and implement it 
+  - EUR 50
+
+### MOU wishbone 2019-10-043, received payment on 2021-MAY-5
+
+- <https://bugs.libre-soc.org/show_bug.cgi?id=493> DMI JTAG TAP needed
+  - EUR 150
+
+### MOU coriolis2 2019-10-029, received payment on 2020-DEC-20
+
+- <https://bugs.libre-soc.org/show_bug.cgi?id=178> Coriolis2 tutorial
+  - EUR 500
+
+### MOU wishbone 2019-10-043, received payment on 2020-OCT-01
+
+- <https://bugs.libre-soc.org/show_bug.cgi?id=401> Convert 180nm Test ASIC Mem Layout diagram to SVG
+  - EUR 150
+
+- <https://bugs.libre-soc.org/show_bug.cgi?id=404> Adding nmigen-soc as a dependency needs documentation updated
+  - EUR 100
+
+- <https://bugs.libre-soc.org/show_bug.cgi?id=472> Tutorial and dev page needed for mesa driver 
+  - EUR 100
+
+- <https://bugs.libre-soc.org/show_bug.cgi?id=325> Trap pipe discussion
+  - EUR 500. shared. lkcl (60%, EUR 300), cole (20%, EUR 100), samuel (20%, EUR 100)
+
+- <https://bugs.libre-soc.org/show_bug.cgi?id=351> Virtual Regfile port
+  - EUR 200. shared, lkcl (50%, EUR 100), cole (50%, EUR 100)
+
+### MOU coriolis2 2019-10-029, received payment on 2020-OCT-01
+
+- Coriolis2 documentation and setup scripts, (documentation budget, EUR 200)
+  - <https://bugs.libre-soc.org/show_bug.cgi?id=291>
+  - <https://bugs.libre-soc.org/show_bug.cgi?id=178>
+  - <https://bugs.libre-soc.org/show_bug.cgi?id=320>