X-Git-Url: https://git.libre-soc.org/?a=blobdiff_plain;f=cole.mdwn;h=2fe174ee3fd9fa4e4d30d50437e9456706189f0b;hb=d1c4c5d08320411b1c613e3160d4bcb4906d6224;hp=23349e1441f0974a4c8e4994466115a6a86daf30;hpb=cdd0f8a50f3c15703d8b507333b5df526b86210c;p=libreriscv.git diff --git a/cole.mdwn b/cole.mdwn index 23349e144..2fe174ee3 100644 --- a/cole.mdwn +++ b/cole.mdwn @@ -1,6 +1,6 @@ # Cole Poirier -Apprentice and assistant Project coordinator for Libre-SOC +Former Apprentice at Libre-SOC * [Bugtracker assignments](https://bugs.libre-soc.org/buglist.cgi?email1=colepoirier%40gmail.com&emailassigned_to1=1&emailcc1=1&emailtype1=substring&resolution=---) @@ -48,7 +48,22 @@ submitted but not confirmed paid: ## Paid -# wishbone 2019-10-043 1-OCT-2020 +### MOU coriolis2 2019-10-029, received payment on 2021-MAY-5 + +- determine SRAM block size and implement it + - EUR 50 + +### MOU wishbone 2019-10-043, received payment on 2021-MAY-5 + +- DMI JTAG TAP needed + - EUR 150 + +### MOU coriolis2 2019-10-029, received payment on 2020-DEC-20 + +- Coriolis2 tutorial + - EUR 500 + +### MOU wishbone 2019-10-043, received payment on 2020-OCT-01 - Convert 180nm Test ASIC Mem Layout diagram to SVG - EUR 150 @@ -65,7 +80,7 @@ submitted but not confirmed paid: - Virtual Regfile port - EUR 200. shared, lkcl (50%, EUR 100), cole (50%, EUR 100) -# coriolis2 2019-10-029 1-OCT-2020 +### MOU coriolis2 2019-10-029, received payment on 2020-OCT-01 - Coriolis2 documentation and setup scripts, (documentation budget, EUR 200) -