X-Git-Url: https://git.libre-soc.org/?a=blobdiff_plain;f=cole.mdwn;h=2fe174ee3fd9fa4e4d30d50437e9456706189f0b;hb=f4410d244ed799a34810189becaea6dbed8071da;hp=8a35b67d4190b691cb4401bf534a6ead4ce7f4ba;hpb=1c1ef2a2045b7fdb166e87e3f92a29cdb4383e63;p=libreriscv.git

diff --git a/cole.mdwn b/cole.mdwn
index 8a35b67d4..2fe174ee3 100644
--- a/cole.mdwn
+++ b/cole.mdwn
@@ -1,6 +1,6 @@
 # Cole Poirier
 
-Apprentice and assistant Project coordinator for Libre-SOC
+Former Apprentice at Libre-SOC
 
 * [Bugtracker assignments](https://bugs.libre-soc.org/buglist.cgi?email1=colepoirier%40gmail.com&emailassigned_to1=1&emailcc1=1&emailtype1=substring&resolution=---)
 
@@ -11,7 +11,6 @@ move things along from one stage to the next
 ## Currently working on
 
 - Reach out to lu_zero of Gentoo about SV POWER binutils
-- <https://bugs.libre-soc.org/show_bug.cgi?id=383> Complete first functional POWER9 Core
 - <https://bugs.libre-soc.org/show_bug.cgi?id=486> Script and document the setup and installation of microwatt dependency on the wiki-HDL_workflow page 
 - <https://bugs.libre-soc.org/show_bug.cgi?id=448> MUL tests
   - shared with lkcl
@@ -43,13 +42,31 @@ move things along from one stage to the next
 
 ## Completed but not yet submitted
 
-- <https://bugs.libre-soc.org/show_bug.cgi?id=401> Convert 180nm Test ASIC Mem Layout diagram to SVG
+## Submitted for NLNet RFP
+
+submitted but not confirmed paid:
+
+## Paid
+
+### MOU coriolis2 2019-10-029, received payment on 2021-MAY-5
+
+- <https://bugs.libre-soc.org/show_bug.cgi?id=502> determine SRAM block size and implement it 
+  - EUR 50
+
+### MOU wishbone 2019-10-043, received payment on 2021-MAY-5
+
+- <https://bugs.libre-soc.org/show_bug.cgi?id=493> DMI JTAG TAP needed
   - EUR 150
 
-- Coriolis2 documentation and setup scripts, (documentation budget, EUR 200)
-  - <https://bugs.libre-soc.org/show_bug.cgi?id=291>
-  - <https://bugs.libre-soc.org/show_bug.cgi?id=178>
-  - <https://bugs.libre-soc.org/show_bug.cgi?id=320>
+### MOU coriolis2 2019-10-029, received payment on 2020-DEC-20
+
+- <https://bugs.libre-soc.org/show_bug.cgi?id=178> Coriolis2 tutorial
+  - EUR 500
+
+### MOU wishbone 2019-10-043, received payment on 2020-OCT-01
+
+- <https://bugs.libre-soc.org/show_bug.cgi?id=401> Convert 180nm Test ASIC Mem Layout diagram to SVG
+  - EUR 150
 
 - <https://bugs.libre-soc.org/show_bug.cgi?id=404> Adding nmigen-soc as a dependency needs documentation updated
   - EUR 100
@@ -63,11 +80,9 @@ move things along from one stage to the next
 - <https://bugs.libre-soc.org/show_bug.cgi?id=351> Virtual Regfile port
   - EUR 200. shared, lkcl (50%, EUR 100), cole (50%, EUR 100)
 
+### MOU coriolis2 2019-10-029, received payment on 2020-OCT-01
 
-## Submitted for NLNet RFP
-
-submitted but not confirmed paid:
-
-### Project 2019-02-012 Date {TEMPLATE INSERT DATE}
-
-## Paid
+- Coriolis2 documentation and setup scripts, (documentation budget, EUR 200)
+  - <https://bugs.libre-soc.org/show_bug.cgi?id=291>
+  - <https://bugs.libre-soc.org/show_bug.cgi?id=178>
+  - <https://bugs.libre-soc.org/show_bug.cgi?id=320>